X86-64 Instruction Encoding: Difference between revisions
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→64-bit SIB byte: New version |
→ModR/M and SIB bytes: New version |
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== ModR/M and SIB bytes == |
== ModR/M and SIB bytes == |
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The ModR/M and SIB bytes |
The ModR/M and SIB bytes are used to encode up to two operands of an instruction, each of which is a direct register or effective memory address. |
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=== ModR/M === |
=== ModR/M === |
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The ModR/M byte encodes a register or an opcode extension, and a register or a memory address |
The ModR/M byte encodes a register or an opcode extension, and a register or a memory address. It has the following fields: |
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<pre> |
<pre> |
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7 0 |
7 0 |
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| MODRM.reg||3 bits||This field can have one of two values: |
| MODRM.reg||3 bits||This field can have one of two values: |
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* A 3-bit opcode extension, which is used by some instructions but has no further meaning other than |
* A 3-bit opcode extension, which is used by some instructions but has no further meaning other than distinguishing the instruction from other instructions. |
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* A 3-bit register reference, which can be used as the source or the destination of an instruction (depending on the instruction). |
* A 3-bit register reference, which can be used as the source or the destination of an instruction (depending on the instruction). The referenced register depends on the [[#Operand-size and address-size override prefix|operand-size]] of the instruction and the instruction itself. See [[#Registers|Registers]] for the values to use for each of the registers. The REX.R, VEX.~R or XOP.~R field can extend this field with 1 most-significant bit to 4 bits total. |
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| MODRM.rm||3 bits||Specifies a direct or indirect register operand, optionally with a displacement. The REX.B, VEX.~B or XOP.~B field can extend this field with 1 most-significant bit to 4 bits total. |
| MODRM.rm||3 bits||Specifies a direct or indirect register operand, optionally with a displacement. The REX.B, VEX.~B or XOP.~B field can extend this field with 1 most-significant bit to 4 bits total. |
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==== Registers ==== |
==== Registers ==== |
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The registers are encoded using the 4-bit values in the X.Reg column of the following table. |
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{| {{wikitable}} |
{| {{wikitable}} |
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! |
! X.Reg!! 8-bit GP!! 16-bit GP!! 32-bit GP!! 64-bit GP!! 64-bit MMX!! 128-bit XMM!! 256-bit YMM!! 16-bit Segment!! 32-bit Control!! 32-bit Debug |
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|- |
|- |
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| 0 |
| 0.000<sub>2</sub> (0)||AL||AX||EAX||RAX||MM0||XMM0||YMM0||ES||CR0||DR0 |
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|- |
|- |
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| 0 |
| 0.001<sub>2</sub> (1)||CL||CX||ECX||RCX||MM1||XMM1||YMM1||CS||CR1||DR1 |
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|- |
|- |
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| 0 |
| 0.010<sub>2</sub> (2)||DL||DX||EDX||RDX||MM2||XMM2||YMM2||SS||CR2||DR2 |
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|- |
|- |
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| 0 |
| 0.011<sub>2</sub> (3)||BL||BX||EBX||RBX||MM3||XMM3||YMM3||DS||CR3||DR3 |
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|- |
|- |
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| 0 |
| 0.100<sub>2</sub> (4)||AH, SPL<span style="vertical-align: super">[[#Table2Note1|1]]</span>||SP||ESP||RSP||MM4||XMM4||YMM4||FS||CR4||DR4 |
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|- |
|- |
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| 0 |
| 0.101<sub>2</sub> (5)||CH, BPL<span style="vertical-align: super">[[#Table2Note1|1]]</span>||BP||EBP||RBP||MM5||XMM5||YMM5||GS||CR5||DR5 |
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|- |
|- |
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| 0 |
| 0.110<sub>2</sub> (6)||DH, SIL<span style="vertical-align: super">[[#Table2Note1|1]]</span>||SI||ESI||RSI||MM6||XMM6||YMM6||invalid||CR6||DR6 |
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|- |
|- |
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| 0 |
| 0.111<sub>2</sub> (7)||BH, DIL<span style="vertical-align: super">[[#Table2Note1|1]]</span>||DI||EDI||RDI||MM7||XMM7||YMM7||invalid||CR7||DR7 |
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|- |
|- |
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| 1 |
| 1.000<sub>2</sub> (8)||R8L||R8W||R8D||R8||MM0||XMM8||YMM8||ES||CR8||DR8 |
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|- |
|- |
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| 1 |
| 1.001<sub>2</sub> (9)||R9L||R9W||R9D||R9||MM1||XMM9||YMM9||CS||CR9||DR9 |
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|- |
|- |
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| 1 |
| 1.010<sub>2</sub> (10)||R10L||R10W||R10D||R10||MM2||XMM10||YMM10||SS||CR10||DR10 |
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|- |
|- |
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| 1 |
| 1.011<sub>2</sub> (11)||R11L||R11W||R11D||R11||MM3||XMM11||YMM11||DS||CR11||DR11 |
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|- |
|- |
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| 1 |
| 1.100<sub>2</sub> (12)||R12L||R12W||R12D||R12||MM4||XMM12||YMM12||FS||CR12||DR12 |
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|- |
|- |
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| 1 |
| 1.101<sub>2</sub> (13)||R13L||R13W||R13D||R13||MM5||XMM13||YMM13||GS||CR13||DR13 |
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|- |
|- |
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| 1 |
| 1.110<sub>2</sub> (14)||R14L||R14W||R14D||R14||MM6||XMM14||YMM14||invalid||CR14||DR14 |
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|- |
|- |
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| 1 |
| 1.111<sub>2</sub> (15)||R15L||R15W||R15D||R15||MM7||XMM15||YMM15||invalid||CR15||DR15 |
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<small id="Table2Note1">1: When any REX prefix is used, SPL, BPL, SIL and DIL are used. Otherwise, without any REX prefix AH, CH, DH and BH are used.</small> |
<small id="Table2Note1">1: When any REX prefix is used, SPL, BPL, SIL and DIL are used. Otherwise, without any REX prefix AH, CH, DH and BH are used.</small> |
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=== SIB === |
=== SIB === |
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The SIB byte has the following fields: |
The SIB byte has the following fields: |
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<pre> |
<pre> |
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! factor ''s'' |
! factor ''s'' |
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|- |
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| 00<sub>2</sub> (0)||1 |
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! b00||1 |
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|- |
|- |
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| 01<sub>2</sub> (1)||2 |
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! b01||2 |
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| 10<sub>2</sub> (2)||4 |
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! b10||4 |
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| 11<sub>2</sub> (3)||8 |
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! b11||8 |
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