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<div class="center" style="width: auto; margin-left: auto; margin-right: auto;">Warning: Many parts of RISC-V are not yet finally. Things might and will change! Look at the official specification for the most up-to-date information</div>
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== Register set ==
RISC-V base ISA consists of 32 general purpose registers of size X bits, given X could be 32, 64 and 128-bits, depending on your base ISA. Beware that some variants may reduce the set of general purpose registers.
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* [https://github.com/riscv/riscv-asm-manual/blob/master/riscv-asm.md RISC-V Assembly Programmer's Manual]
[[:Category:RISC-V]]
[[Category:User drafts]]
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