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User:Lionel/MSR Draft (view source)

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Diddling with table format
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(Diddling with table format)
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{| class="wikitable sortable"
|-
! MSR Number
! MSR Name
! Address
! VendorAccess
! Originator
! class="unsortable" | Bit / Description▼
! class="unsortable" | Description/Comments.
▲! class="unsortable" | Bit / DescriptionAvailability
|-
| 0x00000000
| IA32_P5_MC_ADDR (P5_MC_ADDR)
| 0x0
| Intel
| See Section 35.20 of Intel Architecture Manual 3c, “MSRs in Pentium Processors.”
|
| Pentium Processor (05_01H)
; Intel: Family = 05 Model >= 1
|-
| 0x0000001B
| IA32_APIC_BASE (APIC_BASE)
| 0x1B
| Intel / AMD
| See Intel Architecture Manual 3c.
|
|; Intel : Family = 06 Model = 1 and after supportnewer<br this./>Others!
; AMD : Unknown
|-
| 0x0000003A
| IA32_FEATURE_CONTROL
| Read/Write
| 0x3A
| Intel
| Control CPU Features in Intel 64 Processor (R/W)
|
|;All: If CPUID.01H: ECX[bit 5 or bit 6] = 1
|-
| 0x000000FF
 
| IA32_SAMPLE_AMD
| 0xFF
| AMD
| N/A
|
| N/A
; AMD: Unknown
|-
| 0x00001107
 
| FCR
| RW▼
| ecx: 1107h, eax: FCRValue
| VIA
| R/W Feature Control Register, eax = 2FCRValue▼
▲| RW
|
| Feature Control Register
; VIA: Unknown
|-
| 0x00001108
| FCR2
| Read/Write
| ecx: 1108h, edx: FCR2_Hi, eax: FCRValue▼
| VIA
▲| ecx:RW 1108hFeature Control Register 2, edx: = FCR2_Hi, eax: = FCRValue
| RW
|
▲| Feature Control Register 2
; VIA: Unknown
|-
| 0x00001109
| FCR3
| Write Only
| ecx: 1109h, edx: FCR3_Hi, eax: FCRValue▼
| VIA
▲| ecx:Feature 1109hControl Register 3, edx: = FCR3_Hi, eax: = FCRValue
| WO
|
| Feature Control Register 3
; VIA: Unknown
|}
Brendan
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