User:Lionel/MSR Draft: Difference between revisions
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(Diddling with table format) |
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{| class="wikitable sortable"
|-
! MSR Number
! MSR Name
!
! Originator
! class="unsortable" | Bit / Description▼
! class="unsortable" | Description/Comments
|-
| 0x00000000
| IA32_P5_MC_ADDR (P5_MC_ADDR)
|
| Intel
| See Section 35.20 of Intel Architecture Manual 3c, “MSRs in Pentium Processors.”
|
; Intel: Family = 05 Model >= 1
|-
| 0x0000001B
| IA32_APIC_BASE (APIC_BASE)
|
| Intel
| See Intel Architecture Manual 3c.
|
; AMD : Unknown
|-
| 0x0000003A
| IA32_FEATURE_CONTROL
| Read/Write
| Intel
| Control CPU Features
|
|-
| 0x000000FF
| IA32_SAMPLE_AMD
|
| AMD
| N/A
|
; AMD: Unknown
|-
| 0x00001107
| FCR
| VIA
▲| RW
|
; VIA: Unknown
|-
| 0x00001108
| FCR2
| Read/Write
| ecx: 1108h, edx: FCR2_Hi, eax: FCRValue▼
| VIA
|
▲| Feature Control Register 2
; VIA: Unknown
|-
| 0x00001109
| FCR3
| Write Only
| ecx: 1109h, edx: FCR3_Hi, eax: FCRValue▼
| VIA
|
; VIA: Unknown
|}
| |||
Revision as of 17:36, 23 May 2015
A prototype of a list of MSR's, lifted straight from the manual.
MSR's
| MSR Number | MSR Name | Access | Originator | Description/Comments | Availability |
|---|---|---|---|---|---|
| 0x00000000 | IA32_P5_MC_ADDR (P5_MC_ADDR) | Intel | See Section 35.20 of Intel Architecture Manual 3c, “MSRs in Pentium Processors.” |
| |
| 0x0000001B | IA32_APIC_BASE (APIC_BASE) | Intel | See Intel Architecture Manual 3c. |
| |
| 0x0000003A | IA32_FEATURE_CONTROL | Read/Write | Intel | Control CPU Features |
|
| 0x000000FF | IA32_SAMPLE_AMD | AMD | N/A |
| |
| 0x00001107 | FCR | VIA | R/W Feature Control Register, eax = FCRValue |
| |
| 0x00001108 | FCR2 | Read/Write | VIA | RW Feature Control Register 2, edx = FCR2_Hi, eax = FCRValue |
|
| 0x00001109 | FCR3 | Write Only | VIA | Feature Control Register 3, edx = FCR3_Hi, eax = FCRValue |
|