User:Lionel/MSR Draft: Difference between revisions
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| 0x1B |
| 0x1B |
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| See Intel Architecture Manual 3c. |
| See Intel Architecture Manual 3c. |
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| Intel Family 06 Model 1 Supports this. |
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| 06_01H |
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Revision as of 01:58, 23 May 2015
A prototype of a list of MSR's, lifted straight from the manual.
General
| MSR | Address | Bit \ Description | Comments. |
|---|---|---|---|
| IA32_P5_MC_ADDR (P5_MC_ADDR) | 0x0 | See Section 35.20 of Intel Architecture Manual 3c, “MSRs in Pentium Processors.” | Pentium Processor (05_01H) |
| IA32_APIC_BASE (APIC_BASE) | 0x1B | See Intel Architecture Manual 3c. | Intel Family 06 Model 1 Supports this. |
Intel Specific
| MSR | Address | Bit \ Description | Comments. |
|---|---|---|---|
| IA32_FEATURE_CONTROL | 0x3A | Control Features in Intel 64 Processor (R/W) | If CPUID.01H: ECX[bit 5 or bit 6] = 1 |
AMD Specific
| MSR | Address | Bit Description | Purpose |
|---|
VIA Specific
| MSR | Address | Bit Description | Purpose |
|---|