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User:Greasemonkey/Intel GenX: Difference between revisions
GTT is working
(blitting; me crying about the GTT not working) |
(GTT is working) |
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Note, if you want clipping, you'll want to run an XY_SETUP_CLIP_BLT command, and then enable the "clipping enable" flag.
==Making the GTT behave==
===Memory-to-GPU blit===▼
Tested on:
* GM45 1366x768 CQ60-210TU
===References for GTT page format===
* G45: Vol1a, pg214
===Finding GTTADR===
'''Gen4 only (NOT Gen4.5!)''': 32-bit address "GTTADR" at PCI B0:D2:F0:0x1C. ''(TODO: confirm)''
'''Gen4.5 and above''': 64-bit address "GTTMMADR" at PCI B0:D2:F0:0x18 , then add 2MB (0x200000). ''(TODO: confirm the "above" bit)''
tends to use GTTADR from PCI, which is the 32-bit address at PCI+0x1C.
==
====Gen4.5====
Allocate a block of memory in the stolen memory space. 512KB is the largest you can use for the GTT, and allows for a 512MB virtual addressing space. Ensure that the block of memory is aligned with its size.
Once you have it in place, ensure that the graphics pipeline is flushed (if you don't know what this is, it probably already is flushed), then:
<pre>
genx_reg32[GFX_FLSH_CNTL] = 0;
genx_reg32[PGTBL_CTL] = 1 | gtt_offset; // GTT: 512KB, enabled
genx_reg32[PGTBL_CTL2] = 0; // disables the PPGTT
genx_reg32[GFX_FLSH_CNTL] = 0;
</pre>
We will get to modifying it pretty soon.
*Paging type 0 is for stolen memory.
*Paging type 3 is for main CPU memory. The GPU will snoop the cache for you.
Note that the actual screen is rendered using physical, unmapped "stolen" memory addresses.
Also note that direct access to the stolen memory via GMADR also uses the physical unmapped addresses.
====Gen6====
''TODO: Actually test this and make it work''
Don't allocate it. The chip allocates it for you. Just leave the upper 31:12 in PGTBL_CTL intact when you mess with it. Once you have identity paging in place, set the lower bit.
Consult your manual for what the paging types are actually for. Note, they will be called 1 and 2.
===Identity paging===
In this example, genx_gtt32 points to GTTADR as calculated.
The GPU will handle all the caching issues for you if you use GTTADR. To add to this, in Gen6 this is the only way to access the GTT, so instead of learning the older method of writing via system RAM and then flushing the GPU's cache, you should just use this instead.
<pre>
for(i = 0; i < 512*256; i++)
genx_gtt32[i] = (((i)<<12) | (3<<1) | (1<<0));
</pre>
▲===Memory-to-GPU blit===
''TODO:
==See Also==
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* [https://01.org/linuxgraphics/documentation/driver-documentation-prms Official documentation from Intel]
* [http://www.x.org/docs/intel/ Official documentation on X.org] - covers up to 2012, but also has Vol_1b_G45_core.pdf which is missing from the official Intel PRM list
* Chipset datasheets:
** [http://www.intel.com/Assets/PDF/datasheet/320122.pdf Mobile Intel 4 Series Datasheet] - covers the mobile version of Gen4.5.
* [http://forums.entechtaiwan.com/index.php?topic=2578.0 1366x768 LCD timings] - thread with several different sets of timings
* [http://en.wikipedia.org/wiki/List_of_Intel_graphics_processing_units List of Intel graphics processing units] on Wikipedia - useful for finding out PCI device IDs and exactly what generation you're using.
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