Universal Host Controller Interface

Universal Host Controller Interface (UHCI) was created by Intel as an implementation of the USB 1.0 host controller interface. Along with OHCI, it makes up the USB 1.0 standard.

Technical Details

The UHCI specification defines a set of I/O mapped registers that allow communication between the controller and the operating system. The base address for these registers can be found by searching the PCI controller for a specific VendorID/DeviceID combination, or for a specific ClassID/SubclassID/Interface combination. All UHCI PCI controllers will have a Class ID of 0x0C, a Subclass ID of 0x03, and an Interface value of 0x00. The PCI Configuration space for this device will contain the I/O port address information in BAR4. This may be different from other standards such as OHCI or EHCI.

I/O Registers

Offset (Hex)	Name	Description
00	USBCMD	Usb Command
02	USBSTS	Usb Status
04	USBINTR	Usb Interrupt Enable
06	FRNUM	Frame Number
08	FRBASEADD	Frame List Base Address
0C	SOFMOD	Start Of Frame Modify
10	PORTSC1	Port 1 Status/Control
12	PORTSC2	Port 2 Status/Control

Command Register

Bits	Name	Description
15-8	Reserved
7	Max Packet
6	Configure
5	Software Debug
4	Global Resume
3	Global Suspend
2	Global Reset
1	Host Controller Reset
0	Run

Status Register

Bits	Name	Description
15-6	Reserved
5	Halted
4	Process Error
3	System Error
2	Resume Detected
1	Error Interrupt
0	Interrupt

Interrupt Enable Register

Bits	Name	Description
15-4	Reserved
3	Short Packet
2	Complete
1	Resume
0	Timeout CRC

Port 1/2 Status/Control Registers

Bits	Name	Description
15-13	Reserved
12	Suspend
11-10	Reserved
9	Reset
8	Low Speed
7	Reserved	(Must be 1)
6	Resume Detected
5-4	Line Status
3	Port Enable Changed
2	Port Enabled
1	Connected Changed
0	Connected

Frame List Entry

Bits	Name	Description
31-4	First Descriptor Address
3	Reserved
2	Process Full Queue
1	0 = next entry is TD 1 = next entry is QH
0	Is Empty

UHCI Descriptor

Offset (Hex)	Name	Description	Lenght
00	Next Descriptor	Same as Frame Entry Above	4 byte lenght
04	Status	See below	4 byte lenght
08	Packet Header	See below	4 byte lenght
12	Buffer Address	32-bit address of data buffer	4 byte lenght
16	System Use	128-bit area reserved for use by the system	16 byte lenght

UHCI Descriptor Status

Bits	Name	Description
31-30	Reserved
29	Short Packet Detect
28-27	Error Counter
26	Low Speed
25	Is Isochronous
24	Interrupt On Complete
23	Active	Set by UHCI Controller
22	Stalled	Set by UHCI Controller
21	Data Buffer Error	Set by UHCI Controller
20	Babble Detected	Set by UHCI Controller
19	Non-Acknowledged	Set by UHCI Controller
18	Timeout CRC	Set by UHCI Controller
17	Bit Stuff Error	Set by UHCI Controller
16-11	Reserved
10-0	Actual Length

UHCI Descriptor Packet Header

Bits	Name	Description
31-21	Maximum Length	(Length - 1) so 7 for low speed, 63 for full speed
20	Reserved
19	Data Toggle
18-15	Endpoint
14-8	Device
7-0	Packet Type	0x69 = IN, 0xE1 = OUT, 0x2D = SETUP, other values are invalid

See Also

External Links

• Intel UHCI standard