Universal Host Controller Interface: Difference between revisions
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=== Frame List Entry === |
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! Bits |
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! Name |
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! Description |
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| 32-4 || Descriptor Address || |
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| 3 || Reserved || |
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| 2 || Process Full Queue || |
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| 1 || Is Queue || |
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| 0 || Is Empty || |
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=== UHCI Descriptor === |
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! Offset (Hex) |
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! Name |
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! Description |
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| 00 || Next Descriptor|| Same as Frame Entry Above |
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| 04 || Status || See below |
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| 08 || Packet Header || See below |
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| 12 || Buffer Address || 32-bit address of data buffer |
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| 16 || System Use || 16-byte area reserved for use by the system |
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[[Category:USB]] |
[[Category:USB]] |
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Revision as of 20:27, 17 April 2017
Universal Host Controller Interface (UHCI) was created by Intel as an implementation of the USB 1.0 host controller interface. Along with OHCI, it makes up the USB 1.0 standard.
Technical Details
The UHCI specification defines a set of I/O mapped registers that allow communication between the controller and the operating system. The base address for these registers can be found by searching the PCI controller for a specific VendorID/DeviceID combination, or for a specific ClassID/SubclassID/Interface combination. All UHCI PCI controllers will have a Class ID of 0x0C, a Subclass ID of 0x03, and an Interface value of 0x00. The PCI Configuration space for this device will contain the I/O port address information in BAR4. This may be different from other standards such as OHCI or EHCI.
I/O Registers
| Offset (Hex) | Name | Description |
|---|---|---|
| 00 | USBCMD | Usb Command |
| 02 | USBSTS | Usb Status |
| 04 | USBINTR | Usb Interrupt Enable |
| 06 | FRNUM | Frame Number |
| 08 | FRBASEADD | Frame List Base Address |
| 0C | SOFMOD | Start Of Frame Modify |
| 10 | PORTSC1 | Port 1 Status/Control |
| 12 | PORTSC2 | Port 2 Status/Control |
Port 1/2 Status/Control Registers
| Bits | Name | Description |
|---|---|---|
| 15-13 | Reserved | |
| 12 | Suspend | |
| 11-10 | Reserved | |
| 9 | Reset | |
| 8 | Low Speed | |
| 7 | Reserved | (Must be 1) |
| 6 | Resume Detected | |
| 5-4 | Line Status | |
| 3 | Port Enable Changed | |
| 2 | Port Enabled | |
| 1 | Connected Changed | |
| 0 | Connected |
Frame List Entry
| Bits | Name | Description |
|---|---|---|
| 32-4 | Descriptor Address | |
| 3 | Reserved | |
| 2 | Process Full Queue | |
| 1 | Is Queue | |
| 0 | Is Empty |
UHCI Descriptor
| Offset (Hex) | Name | Description |
|---|---|---|
| 00 | Next Descriptor | Same as Frame Entry Above |
| 04 | Status | See below |
| 08 | Packet Header | See below |
| 12 | Buffer Address | 32-bit address of data buffer |
| 16 | System Use | 16-byte area reserved for use by the system |
References
- Copy of Intel UHCI standard from NetBSD.org