Universal Host Controller Interface: Difference between revisions
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Added link to copy of UHCI spec and corrected PCI Configuration space I/O Port Base Address information. Originally it incorrectly stated that base address could be found in BAR0. It is actually found in BAR4 (as per spec). |
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== Technical Details == |
== Technical Details == |
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The UHCI specification defines a set of I/O mapped registers that allow communication between the controller and the operating system. The base address for these registers can be found by searching the PCI controller for a specific VendorID/DeviceID combination, or for a specific ClassID/SubclassID/Interface combination. All UHCI [[PCI]] controllers will have a Class ID of 0x0C, a Subclass ID of 0x03, and an Interface value of 0x00. The PCI Configuration space for this device will contain the I/O port address information in |
The UHCI specification defines a set of I/O mapped registers that allow communication between the controller and the operating system. The base address for these registers can be found by searching the PCI controller for a specific VendorID/DeviceID combination, or for a specific ClassID/SubclassID/Interface combination. All UHCI [[PCI]] controllers will have a Class ID of 0x0C, a Subclass ID of 0x03, and an Interface value of 0x00. The PCI Configuration space for this device will contain the I/O port address information in BAR4. This may be different from other standards such as OHCI or EHCI. |
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== I/O Registers == |
== I/O Registers == |
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[[Category:USB]] |
[[Category:USB]] |
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== References == |
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# Copy of [ftp://ftp.netbsd.org/pub/NetBSD/misc/blymn/uhci11d.pdf Intel UHCI standard] from NetBSD.org |
Revision as of 20:56, 27 May 2014
Universal Host Controller Interface (UHCI) was created by Intel as an implementation of the USB 1.0 host controller interface. Along with OHCI, it makes up the USB 1.0 standard.
Technical Details
The UHCI specification defines a set of I/O mapped registers that allow communication between the controller and the operating system. The base address for these registers can be found by searching the PCI controller for a specific VendorID/DeviceID combination, or for a specific ClassID/SubclassID/Interface combination. All UHCI PCI controllers will have a Class ID of 0x0C, a Subclass ID of 0x03, and an Interface value of 0x00. The PCI Configuration space for this device will contain the I/O port address information in BAR4. This may be different from other standards such as OHCI or EHCI.
I/O Registers
Offset (Hex) | Name | Description |
---|---|---|
00 | USBCMD | Usb Command |
02 | USBSTS | Usb Status |
04 | USBINTR | Usb Interrupt Enable |
06 | FRNUM | Frame Number |
08 | FRBASEADD | Frame List Base Address |
0C | SOFMOD | Start Of Frame Modify |
10 | PORTSC1 | Port 1 Status/Control |
12 | PORTSC2 | Port 2 Status/Control |
References
- Copy of Intel UHCI standard from NetBSD.org