Timer Interrupt Sources

From Brendan post on http://forum.osdev.org/viewtopic.php?p=277285&sid=e5be2757dbd0ffdab02081df2bec8863#p277285

RTC

Discovery: Standard (assumed to exist)

Calibration: Not necessary

Access speed: Slow ISA IO ports

Counter: Not really (1 Hz if you use RTC's date/time)

Fixed frequency IRQ: Yes, up to 8 KHz (125 us) becoming unreliable at faster frequencies

IRQ on terminal count: No

RTC

PIT

Discovery: Standard (assumed to exist, but may be emulated by HPET)

Calibration: Not necessary

Access speed: Slow ISA IO ports (or slow SMM emulation of ISA ports)

Counter: No

Fixed frequency IRQ: Yes, up to 596.591 KHz (1.676 us)

IRQ on terminal count: Yes, 828 ns precision

ACPI Power Management Timer

Discovery: ACPI tables (FADT)

Calibration: Not necessary

Access speed: IO ports (may or may not be "faster, non-ISA IO ports")

Counter: Yes, 24-bit or 32-bit, monotonically increasing at 3.579545 MHz

Fixed frequency IRQ: No

IRQ on terminal count: No

HPET

Discovery: ACPI tables (HPET)

Calibration: Not necessary

Access speed: Fast (typically memory mapped device)

Counter: Yes, 64-bit monotonically increasing at 10 MHz or better

Fixed frequency IRQ: Yes, up to 10 Mhz or better (100 ns or better)

IRQ on terminal count: Yes, 100 ns or better precision

TSC

Discovery: CPUID

Calibration: Yes

Access speed: Very fast (built into CPU)

Counter: Yes, 64-bit monotonically increasing at CPU's clock speed (which can vary on old CPUs)

Fixed frequency IRQ: No

IRQ on terminal count: No

Local APIC timer (older)

Discovery: MP specification table, ACPI tables (APIC/MADT)

Calibration: Yes

Access speed: Very fast (built into CPU)

Counter: No

Fixed frequency IRQ: Yes, depends on CPU's bus/link speed, typically 100 Mhz or better (10 ns or better)

IRQ on terminal count: Yes, depends on CPU's bus/link speed, typically 10 ns or better

Local APIC timer (newer, with TSC deadline mode)

Discovery: MP specification table, ACPI tables (APIC/MADT)

Calibration: Yes

Access speed: Very fast (built into CPU)

Counter: Yes, 64-bit monotonically increasing at CPU's clock speed (which can vary on old CPUs)

Fixed frequency IRQ: No

IRQ on terminal count: Yes, depends on CPU's clock speed, typically 1 ns or better precision

Precision

For counters; ignoring "emulated with something else", the options in order of best precision are: TSC, HPET, ACPI power management timer

For fixed frequency IRQ; ignoring "emulated with something else", the options in order of best precision are: local APIC timer, HPET, PIT, RTC

For IRQ on terminal count (e.g. needed for "tickless"); ignoring "emulated with something else", in order of best precision are: local APIC timer in TSC deadline mode, local APIC timer without TSC deadline mode, HPET, PIT

Emulation

Counters can be emulated in software using a fixed frequency IRQ (e.g. doing "tick++;" in the IRQ handler).

Fixed frequency IRQ can be emulated in software using IRQ on terminal count (e.g. just set the new count to the same value each time).

IRQ on terminal count can be emulated in software using a fixed frequency IRQ (e.g. doing "count--; if(count == 0)" in the IRQ handler).

Notes

A "counter" is something you poll when you need to know how much time has passed (e.g. for file system timestamps, measuring how much CPU time each thread consumed, etc).

For local APIC timer, there's one per CPU. This is important for scalability (rather than many CPUs fighting to access the same single timer).

A good OS would detect which timers exist and determine their capabilities; then use this information to select the best timers to use for each different purposes.