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RTL8169: Difference between revisions
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=== Reset the Chip ===
It is necessary to reset the RTL8169 to put the registers in a known default state, as well as begin powering up the chip. We need to send the reset command to Chip Command register at offset 0x37. The reset bit is at offset 0x10,
ex:
outportb(ioaddr + 0x37, 0x10); /*set the Reset bit (0x10) to the Command Register (0x37)*/
while(inportb(ioaddr + 0x37) & 0x10)
;/*setting a timeout could be useful if the card is problematic*/
== Setting up the Rx Descriptors ==
One of the new features introduced with this new-gen chip is that it is completely
Rx Descriptors are used to tell the NIC where to put packets once
eg:
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{
/* rx_buffer_len is the size (in bytes) that is reserved for incoming packets */
unsigned int OWN = 0x80000000, EOR = 0x40000000; /*
int i;
for(i = 0; i < num_of_rx_descriptors; i++) /* num_of_rx_descriptors can be up to 1024 */
{
if(i == (num_of_rx_descriptors - 1)) /*
else
/* VLAN adjustments are not part of this guide at the moment - leave as zeros for normal operation */
Rx_Descriptors[i].low_buf = (unsigned int)&packet_buffer_address; /*
/*
}
}
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=== RxConfig ===
The
eg:
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== Max Packet Sizes ==
=== Max Transmit Packet Size ===
The MTPS register is located at offset 0xEC and is used for setting the maximum packet size that can be transmitted from the RTL8169. The
eg:
outportb(ioaddr + 0xEC, 0x3B); /*
=== Receive Packet Maximum Size ===
The RMS register is located at offset 0xDA and is used for setting the maximum packet size that can be
eg:
outportw(ioaddr + 0xDA, 0x1FFF); /*
== Full Reset Example ==
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for(i = 0; i < num_of_rx_descriptors; i++) /* num_of_rx_descriptors can be up to 1024 */
{
if(i == (num_of_rx_descriptors - 1)) /*
else
Rx_Descriptors[i].low_buf = (unsigned int)&packet_buffer_address; /*
/*
}
}
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unsigned char mac_address[6];
outportb(ioaddr + 0x37, 0x10); /*
while(inportb(ioaddr + 0x37) & 0x10){} /*
for (i = 0; i < 6; i++)
setup_rx_descriptors();
outportb(ioaddr + 0x50, 0xC0); /*
outportl(ioaddr + 0x44, 0x0000E70F); /* RxConfig = RXFTH: unlimited, MXDMA: unlimited, AAP: set (promisc. mode set) */
outportl(ioaddr + 0x40, 0x03000700); /* TxConfig = IFG: normal, MXDMA: unlimited */
outportw(ioaddr + 0xDA, 0x1FFF); /*
outportb(ioaddr + 0xEC, 0x3B); /* max tx packet size */
/* offset 0x20 == Transmit Descriptor Start Address Register
offset 0xE4 == Receive Descriptor Start Address Register */
outportl(ioaddr + 0x20, (unsigned long)&Tx_Descriptors[0]; /*
outportl(ioaddr + 0xE4, (unsigned long)&Rx_Descriptors[0]; /*
outportb(ioaddr + 0x37, 0x0C); /*
outportb(ioaddr + 0x50, 0x00); /*
}
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