User:Lionel/MSR Draft: Difference between revisions
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Diddling with table format |
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{| class="wikitable sortable" |
{| class="wikitable sortable" |
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! MSR |
! MSR Number |
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! MSR Name |
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! Address |
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! |
! Access |
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! Originator |
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⚫ | |||
! class="unsortable" | Comments |
! class="unsortable" | Description/Comments |
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⚫ | |||
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|- |
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| 0x00000000 |
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| IA32_P5_MC_ADDR (P5_MC_ADDR) |
| IA32_P5_MC_ADDR (P5_MC_ADDR) |
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| Intel |
| Intel |
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| See Section 35.20 of Intel Architecture Manual 3c, “MSRs in Pentium Processors.” |
| See Section 35.20 of Intel Architecture Manual 3c, “MSRs in Pentium Processors.” |
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| Pentium Processor (05_01H) |
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; Intel: Family = 05 Model >= 1 |
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| 0x0000001B |
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| IA32_APIC_BASE (APIC_BASE) |
| IA32_APIC_BASE (APIC_BASE) |
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| Intel |
| Intel |
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| See Intel Architecture Manual 3c. |
| See Intel Architecture Manual 3c. |
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; Intel : Family = 06 Model = 1 and newer<br />Others! |
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; AMD : Unknown |
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|- |
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| 0x0000003A |
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| IA32_FEATURE_CONTROL |
| IA32_FEATURE_CONTROL |
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| Read/Write |
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| 0x3A |
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| Intel |
| Intel |
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| Control Features |
| Control CPU Features |
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;All: If CPUID.01H: ECX[bit 5 or bit 6] = 1 |
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| 0x000000FF |
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| IA32_SAMPLE_AMD |
| IA32_SAMPLE_AMD |
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| AMD |
| AMD |
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| N/A |
| N/A |
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| N/A |
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; AMD: Unknown |
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|- |
|- |
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| 0x00001107 |
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| FCR |
| FCR |
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⚫ | |||
| ecx: 1107h, eax: FCRValue |
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| VIA |
| VIA |
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⚫ | |||
⚫ | |||
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| Feature Control Register |
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; VIA: Unknown |
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|- |
|- |
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| 0x00001108 |
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| FCR2 |
| FCR2 |
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| Read/Write |
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⚫ | |||
| VIA |
| VIA |
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⚫ | |||
| RW |
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⚫ | |||
; VIA: Unknown |
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|- |
|- |
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| 0x00001109 |
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| FCR3 |
| FCR3 |
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| Write Only |
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⚫ | |||
| VIA |
| VIA |
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⚫ | |||
| WO |
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| Feature Control Register 3 |
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; VIA: Unknown |
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|} |
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Revision as of 17:36, 23 May 2015
A prototype of a list of MSR's, lifted straight from the manual.
MSR's
MSR Number | MSR Name | Access | Originator | Description/Comments | Availability |
---|---|---|---|---|---|
0x00000000 | IA32_P5_MC_ADDR (P5_MC_ADDR) | Intel | See Section 35.20 of Intel Architecture Manual 3c, “MSRs in Pentium Processors.” |
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0x0000001B | IA32_APIC_BASE (APIC_BASE) | Intel | See Intel Architecture Manual 3c. |
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0x0000003A | IA32_FEATURE_CONTROL | Read/Write | Intel | Control CPU Features |
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0x000000FF | IA32_SAMPLE_AMD | AMD | N/A |
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0x00001107 | FCR | VIA | R/W Feature Control Register, eax = FCRValue |
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0x00001108 | FCR2 | Read/Write | VIA | RW Feature Control Register 2, edx = FCR2_Hi, eax = FCRValue |
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0x00001109 | FCR3 | Write Only | VIA | Feature Control Register 3, edx = FCR3_Hi, eax = FCRValue |
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