Setting Up Paging With PAE: Difference between revisions
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===Setting Up The Data Structures=== |
===Setting Up The Data Structures=== |
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As mentioned above the 'Page-Directory-Pointer-Table' is added, which contains 4 Page-Directory-Entries |
As mentioned above the 'Page-Directory-Pointer-Table' is added, which contains 4 Page-Directory-Entries |
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< |
<syntaxhighlight lang="c"> |
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uint64_t page_dir_ptr_tab[4] __attribute__((aligned(0x20))); // must be aligned to (at least)0x20, ... |
uint64_t page_dir_ptr_tab[4] __attribute__((aligned(0x20))); // must be aligned to (at least)0x20, ... |
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// ... turning out that you can put more of them into one page, saving memory |
// ... turning out that you can put more of them into one page, saving memory |
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</syntaxhighlight> |
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</source> |
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Keep in mind that the size of the CR3 register remains at 4byte, meaning that a PDPT must be located below 4GiB in physical memory. |
Keep in mind that the size of the CR3 register remains at 4byte, meaning that a PDPT must be located below 4GiB in physical memory. |
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Now we need our Page-Directory. For the sake of easiness, we'll use PSE. (2 MIB pages mapped in page directory) |
Now we need our Page-Directory. For the sake of easiness, we'll use PSE. (2 MIB pages mapped in page directory) |
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< |
<syntaxhighlight lang="c"> |
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// 512 entries |
// 512 entries |
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uint64_t page_dir[512] __attribute__((aligned(0x1000))); // must be aligned to page boundary |
uint64_t page_dir[512] __attribute__((aligned(0x1000))); // must be aligned to page boundary |
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</syntaxhighlight> |
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</source> |
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===Making it run=== |
===Making it run=== |
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Ok, now we have our structures. Let's map the first 2 MIB. |
Ok, now we have our structures. Let's map the first 2 MIB. |
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< |
<syntaxhighlight lang="c"> |
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page_dir_ptr_tab[0] = (uint64_t)&page_dir | 1; // set the page directory into the PDPT and mark it present |
page_dir_ptr_tab[0] = (uint64_t)&page_dir | 1; // set the page directory into the PDPT and mark it present |
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page_dir[0] = 0b10000011; //Address=0, 2MIB, RW and present |
page_dir[0] = 0b10000011; //Address=0, 2MIB, RW and present |
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</syntaxhighlight> |
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</source> |
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Pages are mapped. Now we have to set the PAE-bit in CR4 and load the PDPT into CR3 |
Pages are mapped. Now we have to set the PAE-bit in CR4 and load the PDPT into CR3 |
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< |
<syntaxhighlight lang="c"> |
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asm volatile ("movl %%cr4, %%eax; bts $5, %%eax; movl %%eax, %%cr4" ::: "eax"); // set bit5 in CR4 to enable PAE |
asm volatile ("movl %%cr4, %%eax; bts $5, %%eax; movl %%eax, %%cr4" ::: "eax"); // set bit5 in CR4 to enable PAE |
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asm volatile ("movl %0, %%cr3" :: "r" (&page_dir_ptr_tab)); // load PDPT into CR3 |
asm volatile ("movl %0, %%cr3" :: "r" (&page_dir_ptr_tab)); // load PDPT into CR3 |
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</syntaxhighlight> |
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</source> |
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Finally, we'll enable paging. |
Finally, we'll enable paging. |
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Simply done: |
Simply done: |
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< |
<syntaxhighlight lang="c"> |
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asm volatile ("movl %%cr0, %%eax; orl $0x80000000, %%eax; movl %%eax, %%cr0;" ::: "eax"); |
asm volatile ("movl %%cr0, %%eax; orl $0x80000000, %%eax; movl %%eax, %%cr0;" ::: "eax"); |
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</syntaxhighlight> |
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</source> |
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PAE paging should now be enabled. |
PAE paging should now be enabled. |