Serial Ports: Difference between revisions

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===First In First Out Control Register===

The First In / First Out Control Register (FCR) is for controlling the FIFO buffers. Access this register by writing to port offset +3.

{| class="wikitable"

|-

! Bits 7-6

! Bits 5-4

! Bit 3

! Bit 2

! Bit 1

! Bit 0

|-

| Interrupt Trigger Level

| Reserved

| DMA Mode Select

| Clear Transmit FIFO

| Clear Receive FIFO

| Enable FIFO's

|}

====Clear Transmit FIFO and Clear Receive FIFO====

Bit 2 being set clears the Transmit FIFO buffer while Bit 1 being set clears the Receive FIFO buffer. Both bits will set themselves back to 0 after they are done being cleared.

====Interrupt Trigger Level====

The Interrupt Trigger Level is used to configure how much data must be received in the FIFO Receive buffer before triggering a Received Data Available Interrupt.

{| {{wikitable}}

! Bit 7

! Bit 6

! Trigger Level

|-

| 0 || 0 || 1 Byte

|-

| 0 || 1 || 4 Bytes

|-

| 1 || 0 || 8 Bytes

|-

| 1 || 1 || 14 Bytes

|}

===Interrupt Identification Register===

The Interrupt Identification Register (IIR) is for identifying pending interrupts. Access this register by reading from port offset +3.

{| class="wikitable"

|-

! Bits 7-6

! Bits 5-4

! Bit 3

! Bit 2-1

! Bit 0

|-

| FIFO Buffer State

| Reserved

| Timeout Interrupt Pending (UART 16550) or Reserved

| Interrupt State

| Interrupt Pending

|}

====Interrupt State====

After Interrupt Pending is set, the Interrupt State shows the interrupt that has occurred. They have varying levels of priority, with high-value interrupts handled first, and low-value interrupts being handled last.

{| {{wikitable}}

! Bit 7

! Bit 6

! Interrupt

! Priority

|-

| 0 || 0 || Modem Status || 4 (Lowest)

|-

| 0 || 1 || Transmitter Holding Register Empty || 3

|-

| 1 || 0 || Received Data Available || 2

|-

| 1 || 1 || Receiver Line Status || 1 (Highest)

|}

====FIFO Buffer State====

{| {{wikitable}}

! Bit 2

! Bit 1

! State

|-

| 0 || 0 || No FIFO

|-

| 0 || 1 || FIFO Enabled but Unusable

|-

| 1 || 0 || FIFO Enabled

===Line Status Register===