Serial Ports: Difference between revisions

===Modem Control Register===

The Modem Control Register is one half of the hardware handshaking registers.

While most serial devices no longer use hardware handshaking, The lines are still included in all 16550 compatible UARTS.

These can be used as general purpose output ports, or to actually perform handshaking.

By writing to the Modem Control Register, it will set those lines active.

{| {{wikitable}}

! Bit

! Name

! Meaning

|-

| 0 || Data Terminal Ready (DTR) || Controls the Data Terminal Ready Pin

|-

| 1 || Request to Send (RTS) || Controls the Request to Send Pin

|-

| 2 || Out 1 || Controls a hardware pin (OUT2) which is unused in PC implementations

|-

| 3 || Out 2 || Controls a hardware pin (OUT2) which is unused in PC implementations

|-

| 4 || Loop || Provides a local loopback feature for diagnostic testing of the UART

|-

| 5 || 0 || Unused

|-

| 6 || 0 || Unused

|-

| 7 || 0 || Unused

|}

While the two OUT pins are unused in PC implementations, they could be used for status LED's in certain instances however, they are never wired to the serial port itself.

Loopback mode is a diagnostic feature. When bit 4 is set to logic 1,

the following occur the transmitter Serial Output (SOUT) is set to the Marking (logic 1) state; the receiver Serial

Input (SIN) is disconnected; the output of the Transmitter Shift Register is ‘‘looped back’’ into the Receiver Shift

Register input; the four MODEM Control inputs (DSR, CTS, RI, and DCD) are disconnected; and the four

MODEM Control outputs (DTR, RTS, OUT 1, and OUT 2) are internally connected to the four MODEM Control

inputs, and the MODEM Control output pins are forced to their inactive state (high). In the loopback mode, data

that is transmitted is immediately received. This feature allows the processor to verify the transmit-and received-

data paths of the UART. In the loopback mode, the receiver and transmitter interrupts are fully operational. Their sources are external to

the part. The MODEM Control Interrupts are also operational, but the interrupts’ sources are now the lower four

bits of the MODEM Control Register instead of the four MODEM Control inputs. The interrupts are still controlled

by the Interrupt Enable Register.

===Modem Status Register===

This register provides the current state of the control lines from a peripheral device.

In addition to this current-state information, four bits of the MODEM Status Register provide change information.

These bits are set to a logic 1 whenever a control input from the MODEM changes state. They are reset to logic

0 whenever the CPU reads the MODEM Status Register

{| {{wikitable}}

! Bit

! Name

! Meaning

|-

| 0 || Delta Clear to Send (DCTS) || Indicates that CTS input has changed state since the last time it was read

|-

| 1 || Delta Data Set Ready (DDSR) || Indicates that DSR input has changed state since the last time it was read

|-

| 2 || Trailing Edge of Ring Indicator (TERI) || Indicates that RI input to the chip has changed from a low to a high state

|-

| 3 || Delta Data Carrier Detect (DDCD) || Indicates that DCD input has changed state since the last time it ware read

|-

| 4 || Clear to Send (CTS) || Inverted CTS Signal

|-

| 5 || Data Set Ready (DSR) || Inverted DSR Signal

|-

| 6 || Ring Indicator (RI) || Inverted RI Signal

|-

| 7 || Data Carrier Detect (DCD) || Inverted DCD Signal

|}

If Bit 4 of the MCR (LOOP bit) is set, the upper 4 bits will mirror the 4 status output lines set in the Modem Control Register.