Serial Ports: Difference between revisions
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| [unchecked revision] | [unchecked revision] |
Content deleted Content added
Added First In / First Out Control Register and Interrupt Identification Register Sections (plus minor consistency edit) |
m Fix mistake in Interrupt State section and flip table for bits 2-1 and 7-6 |
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! Bit |
! Bit 2 |
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! Bit |
! Bit 1 |
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! Interrupt |
! Interrupt |
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! Priority |
! Priority |
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====FIFO Buffer State==== |
====FIFO Buffer State==== |
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{| {{wikitable}} |
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! Bit |
! Bit 7 |
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! Bit |
! Bit 6 |
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! State |
! State |
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