SYSENTER: Difference between revisions
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'''Note that the Kernel does not automatically have a kernel stack loaded. This is the handler's responsibility.'''
SYSRET loads CS from STAR 63:48. It loads EIP from ECX and SS from STAR 63:48 + 8.
'''Note that the User stack is not automatically loaded. Also note that ECX must be preserved.'''
====64 bit mode====
The operation in 64 bit mode is the same, except that RIP is loaded from LSTAR, or CSTAR of in IA32-e submode (A.K.A. compatibility mode). It also respectively saves and loads RFLAGS to and from R11.
'''In Long Mode, userland CS will be loaded from STAR 63:48 + 16 and userland SS from STAR 63:48 + 8 on SYSRET. You may need to modify your GDT accordingly.'''
Moreover, SYSRET will return to compatibility mode if the operand size is set to 32 bits, which is, for instance, nasm's default. To explicitly request a return into long mode, set the operand size to 64 bits (e.g. "o64 sysret" with nasm).
==Compatibility across Intel and AMD==
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All Intel CPUs to date (2013) have a silicon bug when executing the SYSRET instruction. If a non-canonical address is present in RCX when executing SYSRET, a General Protection Fault will be taken in CPL0 with CPL3 registers. See [http://lists.xen.org/archives/html/xen-announce/2012-06/msg00001.html Xen Security Advisory 7] for more details.
[[Category:X86 CPU]]
[[de:Syscall/sysret]]
==See also==
===External Links===
*https://cdrdv2.intel.com/v1/dl/getContent/671200 Page 1882 for SYSRET
[[Category:System Calls]]
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