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SSE: Difference between revisions
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=== Checking for SSE ===
to check for SSE CPUID.01h:EDX.SSE[bit 25] needs to be set
<
mov eax, 0x1
cpuid
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jz .noSSE
;SSE is available
</syntaxhighlight>
=== Adding support ===
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Here is an asm example:
<
;now enable SSE and the like
mov eax, cr0
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mov cr4, eax
ret
</syntaxhighlight>
=== FXSAVE and FXRSTOR ===
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Example usage:
<
char fxsave_region[512] __attribute__((aligned(16)));
asm volatile(" fxsave %0 "::"m"(fxsave_region));
</syntaxhighlight>
or in asm:
<
segment .code
SaveFloats:
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align 16
SavedFloats: TIMES 512 db 0
</syntaxhighlight>
Pitfalls: only one level of saving supported.
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The bit for XSAVE (needed to manage extended processor states) can be found on CPUID page 1, in ECX bit 26
======AVX2======
The bit for AVX2 can be found on CPUID page 7, 0, in
=====AVX-512=====
The bits for AVX-512 are in CPUID page 0x0D, 0x0, EAX bits 5-7
AVX512 implements separate features that can also be detected in CPUID page 7, 0. Basic support is detected by checking the AVX512F Bit (AVX-512 Foundation) in CPUID page 7, 0 EBX Bit 16, you can also check various AVX512 Features through the same CPUID Function, the bits are listed [[w:CPUID|here]]
===X86_64===
When the [[X86-64]] architecture was introduced, AMD demanded a minimum level of SSE support to simplify OS code. Any system capable of long mode should support at least SSE and SSE2, which means that the kernel does not need to care about the old FPU save code.
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Here is an example of assembly code enabling AVX after SSE has been enabled (you should check AVX and XSAVE are supported first, see above):
<
enable_avx:
push rax
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pop rax
ret
</syntaxhighlight>
To enable AVX-512, set the OPMASK (bit 5), ZMM_Hi256 (bit 6), Hi16_ZMM (bit 7) of XCR0. You must ensure that these bits are valid first (see above).
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