RTL8139: Difference between revisions
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[[Image:rtl8139.JPG|right|frame|A PCI RTL8139]] |
[[Image:rtl8139.JPG|right|frame|A PCI RTL8139]] |
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=Programming Guide= |
== Programming Guide == |
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== Turning on the RTL8139 == |
=== Turning on the RTL8139 === |
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Send 0x00 to the CONFIG_1 register (0x52) to set the LWAKE + LWPTN to active high. |
Send 0x00 to the CONFIG_1 register (0x52) to set the LWAKE + LWPTN to active high. |
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this should essentially *power on* the device. |
this should essentially *power on* the device. |
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=== Software Reset! === |
==== Software Reset! ==== |
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Next, we should do a software reset to clear the RX and TX buffers and set everything |
Next, we should do a software reset to clear the RX and TX buffers and set everything |
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the reset. If the RST bit is high (1), then the reset is still in operation. |
the reset. If the RST bit is high (1), then the reset is still in operation. |
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=== Init Receive buffer === |
==== Init Receive buffer ==== |
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For this part, we will send the chip a memory location to use as its receive buffer start |
For this part, we will send the chip a memory location to use as its receive buffer start |
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outportd(0x30, (unsigned long)rx_buffer); // send dword memory location to RBSTART (0x30) |
outportd(0x30, (unsigned long)rx_buffer); // send dword memory location to RBSTART (0x30) |
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== Set IMR + ISR == |
=== Set IMR + ISR === |
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The Interrupt Mask Register (IMR) and Interrupt Service Register (ISR) are responsible |
The Interrupt Mask Register (IMR) and Interrupt Service Register (ISR) are responsible |
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01000101: Confirmed. In fact, the only way to clear an interrupt is by writing to it. The datasheet says that reading is what you must do, but it is completely wrong. |
01000101: Confirmed. In fact, the only way to clear an interrupt is by writing to it. The datasheet says that reading is what you must do, but it is completely wrong. |
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== Configuring receive buffer (RCR) == |
=== Configuring receive buffer (RCR) === |
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Before hoping to see a packet coming to you, you should tell the RTL8139 to '''accept''' packets based on various rules. The configuration register is RCR. |
Before hoping to see a packet coming to you, you should tell the RTL8139 to '''accept''' packets based on various rules. The configuration register is RCR. |
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outportl(0x44, 0xf | (1 << 7)); // (1 << 7) is the WRAP bit, 0xf is AB+AM+APM+AAP |
outportl(0x44, 0xf | (1 << 7)); // (1 << 7) is the WRAP bit, 0xf is AB+AM+APM+AAP |
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== Enable Receive and Transmitter == |
=== Enable Receive and Transmitter === |
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Now is the time to start up the RX and TX functions. |
Now is the time to start up the RX and TX functions. |
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