RISC-V: Difference between revisions
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==== Changing privilege ====
In RISC-V, the privilege mode of a ''hart'' can be changed by:
* A trap or interrupt
* The execution of the `mret` or `sret` instructions
* Intervention by a hardware debugger
* A hart being reset (it always starts in Machine mode)
When a trap or interrupt occurs, the ''hart'' determines which privilege mode will catch this exception and jump to the address stored in <code>mtvec</code> or <code>stvec</code>, possibly with an offset, for exceptions caught by Machine and Supervisor mode respectively. This mode with an offset into an [https://en.wikipedia.org/wiki/Interrupt_vector_table interrupt vector table] is called vectored interrupts. RISC-V traps do not use an offset. This has the side effect of making the interrupt vector table a table of jump instructions as opposed to a table of addresses.
The `mret` and `sret` instructions update the privilege mode to that specified by `mstatus` or `sstatus` before resuming in said mode at `mepc` or `sepc` respectively. These instructions are intended for returning from trap/interrupt handlers and explicit privilege mode switches.▼
▲The
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