RISC-V: Difference between revisions
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RISC-V is not a single ISA, rather a meta-ISA. It defines basics and boundaries for a family of implementations.
The specification is published under a Creative
architectures unwieldy to manufacture and design around.
An implementation consists of one of the [[#Base ISA|Base ISAs]] and zero or more [[#Extensions|Extensions]].
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=== Hardware Threads ===
The RISC-V ISA specifies hardware threads,
A processor may contain multiple ''harts'' and has at least one.
Each hart has an ID associated with it and at least one ''hart'' has ID 0.
=== Exceptions, Traps and Interrupts ===
In RISC-V the term ''Exception'' refers to an unusual condition at run-time associated with an instruction in the current hardware thread.<br/>
A ''Trap'' is a synchronous transfer of control to a trap handler and is caused by an exceptional condition within a RISC-V thread. The trap handlers usually execute in a more privileged environment.<br/>
An external event that occurs asynchronously to the current thread will cause an ''Interrupt''. When an interrupt occurs,
===
The spec defines a debug mode and 4 privilege modes, of which a valid combination has to be implemented. The modes are:
{| class="wikitable"
|Debug
| Mode for ''complete'' control, for debuggers
|-
| Machine
| Mode with nearly full control, no debug registers (think firmware), not optional
|-
| Hypervisor
| VM-Hypervisor
|-
| Supervisor
| OS-level
|-
| User
| Application-level, lowest privilege
|}
====
Valid combinations of privilege levels are:
* One level: Machine mode only for embedded systems
* Two levels: Machine and User mode, small systems
* Three levels: Machine, Supervisor and User mode, complex systems able to run Unix-like operating systems
* Four levels: Machine, Hypervisor, Virtual supervisor and User mode, complex systems supporting virtualization in hardware
====
In RISC-V, the privilege mode of a ''hart'' can be changed by:
* A trap or interrupt in the thread caught by a higher privilege mode
* The execution of the <code>mret</code> or <code>sret</code> instructions
* Intervention by a hardware debugger
* A hart being reset (it always starts in Machine mode)
When a trap or interrupt occurs, the ''hart'' determines which privilege mode will catch this exception and jump to the address stored in <code>mtvec</code> or <code>stvec</code>, possibly with an offset, for exceptions caught by Machine and Supervisor mode respectively. This mode with an offset into an [https://en.wikipedia.org/wiki/Interrupt_vector_table interrupt vector table] is called vectored interrupts. RISC-V traps do not use an offset. This has the side effect of making the interrupt vector table a table of jump instructions as opposed to a table of addresses.
The <code>mret</code> and <code>sret</code> instructions update the privilege mode to that specified by <code>mstatus</code> or <code>sstatus</code> respectively before resuming in said mode at the address stored in <code>mepc</code> or <code>sepc</code> respectively. These instructions are intended for returning from trap/interrupt handlers and explicit privilege mode switches.
The base ISA specifies RV32I and RV64I, 32 and 64-bit respectively; most of what is said about RV32I also applies to RV64I. Additionally, there is also RV32E, a reduced version of RV32I for embedded systems, and RV128I, a 128-bit version, which is mostly a placeholder so far.
==== RV32I ====
RV32I offers 31 general-purpose registers (x1-x31) which hold integer values, while the x0 register is hardwired to zero; all registers are 32 bits wide. It specifies a number of logical and arithmetic operations (and, or, xor, shift left and right, addition and subtraction), all of which are available with a source register or an immediate.
==== RV32E ====
RV32E reduces the number of general-purpose registers to 15 (x1-x15), and x0 is still hardwired to constant zero.
==== RV64I ====
RV64I is very similar to its 32-bit counterpart, but offers 64-bit wide registers and can read the CSRs in one operation instead of requiring the programmer to read the upper and lower half separately. Additionally, there are some instructions to work with words (32 bit) instead of double-words.
==== RV128I ====
Like RV64I but with 128bit register length. This base ISA is not ratified and no widely adopted CPUs that support RV128I exist.
== Extensions ==
An extension can be one of the officially defined ones or a vendor-specific one (there is opcode space explicitly reserved for this) and can define additional elements, including opcodes and registers.
The following Standard Extensions are noteworthy here:
==== Zicsr ====
This extensions defines some kind of secondary address space for '''Control and Status Register''', which
These registers can be accessed via the ''CSR instructions''.
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==== RVF & RVD & RVQ (Floating Point Extensions) ====
Adds additional instructions to work with floating points and also the floating point registers.
The different extensions differ in the length
==== RVV (Vector Instruction Extension) ====
The RISC-V V extension adds a vector register file and instructions for operating on vectors. Note that RISC-V's vectors have a very different model from e.g. x86 in that a vector register's width is an implementation detail of the ''hart'' instead of an ISA-mandated specific size. These vector instructions conceptually work more like a stream of operations rather than operating on a predetermined amount of values in batches. Be warned that there are differences between RVV versions 0.7 and 1.0 which may break some software.
==== C (Compressed Instructions Extension) ====
Allows 16-bit variants of common instructions with a reduced register set (16 instead of 32) and
is
== Running RISC-V ==
=== Emulator, Simulators, etc ===
For advanced setups (multiple privilege modes, etc.), QEMU is probably the way to go. Other simulators [https://riscv.org/software-status/#simulators exist],
but the author has not yet tried them :-)
=== Real Hardware ===
Some fairly inexpensive SoCs are becoming available, notably VisionFive 2 from StartFive [https://doc-en.rvspace.org/Doc_Center/visionfive_2.html] and Star64 form Pine64 [https://wiki.pine64.org/wiki/STAR64].
Both of these are Raspberry Pi like devices based on JH7110 Quad-Core SiFive U74 64-Bit CPU with
MMU, GPU, GPIO, Ethernet, et al and run Linux.
Also note
[https://www.sifive.com/boards/hifive-unleashed HiFive Unleashed], which is also able to run Linux, has
multiple cores, and is expandable.
The PolarFire SoC Icicle Kit [https://www.crowdsupply.com/microchip/polarfire-soc-icicle-kit] by Microchip also contains cores by SiFive and can run Linux, but is cheaper than the HiFive Unleashed.
Most other hardware implementations (which are for sale for normal consumers) are more in the
category of "microcontrollers" and lack parts like a Memory Management Unit (MMU), I/O for humans
(keyboard, graphics, sound), etc.
The Kendryte K210 (e.g. in the MAIX Bit-board) is a RV64IMACFD_Zicsr_Zifence processor with two harts
and quite cheap.
== See Also ==
=== Articles ===
* [[HiFive-1 Bare Bones]]
* [[RISC-V_Bare_Bones|RISC-V Bare Bones]]
* [[RISC-V_Meaty_Skeleton_with_QEMU_virt_board|RISC-V Meaty Skeleton with QEMU virt board]]
=== External Links ===
* [[Wikipedia:RISC-V|RISC-V on Wikipedia]]
* [
* [
* [https://riscv.org/technical/specifications/ RISC-V Specifications]
* [https://github.com/riscv/riscv-asm-manual/blob/master/riscv-asm.md RISC-V Assembly Programmer's Manual]
[[Category:RISC-V]]
[[Category:Instruction Set Architecture]]
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