Protected Mode: Difference between revisions
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(Merged Journey To The Protected Land and Protected Mode and also made a few minor touch-ups) |
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'''Protected mode''' is the main operating mode of modern Intel processors (and clones) since the 80286 ( |
'''Protected mode''' is the main operating mode of modern Intel processors (and clones) since the 80286 (16 bit). On 80386s and later, the 32 bit Protected Mode allows working with several virtual address spaces, each of which has a maximum of 4GB of addressable memory; and enables the system to enforce strict memory and hardware I/O protection as well as restricting the available instruction set via. [[Security#Rings|Rings]]. |
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A CPU that is initialized by the [[BIOS]] starts in [[Real Mode]]. Enabling Protected Mode unleashes the real power of your CPU. However, it will prevent you from using most of the BIOS interrupts, since these work in Real Mode (unless you have also written a [[Virtual 8086 Mode|V86]] monitor). |
A CPU that is initialized by the [[BIOS]] starts in [[Real Mode]]. Enabling Protected Mode unleashes the real power of your CPU. However, it will prevent you from using most of the BIOS interrupts, since these work in Real Mode (unless you have also written a [[Virtual 8086 Mode|V86]] monitor). |
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Before switching to Protected Mode, you have to disable interrupts, including [[Non Maskable Interrupt|NMI]] (as suggested by Intel Developers Manual), possibly enable the [[A20 Line]], and load the [[Global Descriptor Table]] with segment descriptors suitable for code, data, and stack. |
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Before switching to protected mode, you must: |
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*Disable interrupts, including [[Non Maskable Interrupt|NMI]] (as suggested by Intel Developers Manual). |
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*Enable the [[A20 Line]]. |
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*Load the [[Global Descriptor Table]] with segment descriptors suitable for code, data, and stack. |
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This example loads a descriptor table into the processor's GDTR register, and then sets the lowest bit of CR0: |
This example loads a descriptor table into the processor's GDTR register, and then sets the lowest bit of CR0: |
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<source lang="asm"> |
<source lang="asm"> |
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cli ; disable interrupts |
cli ; disable interrupts |
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lgdt [gdtr] ; load GDT register with start address of Global Descriptor Table |
lgdt [gdtr] ; load GDT register with start address of Global Descriptor Table |
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mov eax, cr0 |
mov eax, cr0 |
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or al, 1 ; set PE (Protection Enable) bit in CR0 (Control Register 0) |
or al, 1 ; set PE (Protection Enable) bit in CR0 (Control Register 0) |
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mov cr0, eax |
mov cr0, eax |
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; Perform far jump to selector 08h (offset into GDT, pointing at a 32bit PM code segment descriptor) |
; Perform far jump to selector 08h (offset into GDT, pointing at a 32bit PM code segment descriptor) |
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; to load CS with proper PM32 descriptor) |
; to load CS with proper PM32 descriptor) |
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; [...] |
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PModeMain: |
PModeMain: |
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; load DS, ES, FS, GS, SS, ESP |
; load DS, ES, FS, GS, SS, ESP |
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</source> |
</source> |
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Good Luck |
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==See Also== |
==See Also== |
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*[[Real Mode]] |
*[[Real Mode]] |
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*[[Virtual 8086 Mode]] |
*[[Virtual 8086 Mode]] |
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*[[Journey To The Protected Land]] |
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===External Links=== |
===External Links=== |
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*[http://www.nondot.org/sabre/os/articles/ProtectedMode/ OSRC: protected mode] |
*[http://www.nondot.org/sabre/os/articles/ProtectedMode/ OSRC: protected mode] |
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*http://home.swipnet.se/smaffy/asm/info/embedded_pmode.pdf - pragmatic tutorial on |
*http://home.swipnet.se/smaffy/asm/info/embedded_pmode.pdf - pragmatic tutorial on protected mode ([http://web.archive.org/web/20030604185154/http://home.swipnet.se/smaffy/asm/info/embedded_pmode.pdf Cached copy]) |
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*http://www.osdever.net/tutorials.php?cat=4&sort=1 |
*http://www.osdever.net/tutorials.php?cat=4&sort=1 |
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*http://www.brokenthorn.com/Resources/OSDev8.html |
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*[[Wikipedia:Protected_mode|Protected mode Wikipedia page]] |
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[[Category:X86 CPU]] |
[[Category:X86 CPU]] |
Revision as of 01:23, 4 November 2017
Protected mode is the main operating mode of modern Intel processors (and clones) since the 80286 (16 bit). On 80386s and later, the 32 bit Protected Mode allows working with several virtual address spaces, each of which has a maximum of 4GB of addressable memory; and enables the system to enforce strict memory and hardware I/O protection as well as restricting the available instruction set via. Rings.
A CPU that is initialized by the BIOS starts in Real Mode. Enabling Protected Mode unleashes the real power of your CPU. However, it will prevent you from using most of the BIOS interrupts, since these work in Real Mode (unless you have also written a V86 monitor).
Entering Protected Mode
Before switching to protected mode, you must:
- Disable interrupts, including NMI (as suggested by Intel Developers Manual).
- Enable the A20 Line.
- Load the Global Descriptor Table with segment descriptors suitable for code, data, and stack.
Whether the CPU is in Real Mode or in Protected Mode is defined by the lowest bit of the CR0 or MSW register.
This example loads a descriptor table into the processor's GDTR register, and then sets the lowest bit of CR0:
cli ; disable interrupts
lgdt [gdtr] ; load GDT register with start address of Global Descriptor Table
mov eax, cr0
or al, 1 ; set PE (Protection Enable) bit in CR0 (Control Register 0)
mov cr0, eax
; Perform far jump to selector 08h (offset into GDT, pointing at a 32bit PM code segment descriptor)
; to load CS with proper PM32 descriptor)
jmp 08h:PModeMain
PModeMain:
; load DS, ES, FS, GS, SS, ESP