Paging: Difference between revisions
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===Virtual Address Spaces=== |
===Virtual Address Spaces=== |
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In a paged system, each process may execute in its own 4gb area of memory, without any chance of effecting any other process's memory, or the kernel's. |
In a paged system, each process may execute in its own 4gb area of memory, without any chance of effecting any other process's memory, or the kernel's. |
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[[Image:Virtual memory.png|frame|none|paging illustrated: two process with different views of the same physical memory]] |
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===Virtual Memory=== |
===Virtual Memory=== |
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Revision as of 21:09, 15 November 2007
Overview
Paging is a memory scheme that breaks up memory in groups of pages that are constantly swapped between hard disk and computer. This allows for one to appear as though they have more memory than they actually do.
MMU
Paging is achieved through the use of the MMU. The MMU is a unit that transforms virtual addresses into physical addresses based on the current page table.This section focuses on the x86 MMU.
Overview
On the x86, the MMU maps memory through a series of tables, two to be exact. They are the paging directory, and the paging table.
Both tables contain 1024 4byte entries, making them each 4kb. In the page directory, each entry points to a page table. In the page table, each entry points to a physical address that is then mapped to the virtual address found by calculating the offset within the directory and the offset within the table. This can be done as the entire table system represents a linear 4gb virtual memory map.
Page Directory
The topmost paging structure is the page directory. It is essentially an array of page directory entries that take the following form.
Note: With 5mb pages, bits 21 through 12 are Reserved!
The page table address field represents the physical address of the page table that managers the four megabytes at that point. Please note that it is very important that this address be 4kb aligned. This is needed, due to the fact that the last bits of the dword are overwritten by access bits and such.
The next valid flag, S, or 'Page Size', stores the page size for that specific entry. If the bit is set, then pages are 4mb in size. Otherwise, they are 4kb.
A, or 'Accessed' is used to discover whether a page has been read or written to. If it has, then the bit is set, otherwise, it is not. Note that, this bit will not be cleared by the CPU, so that burden falls on the OS. (ie. if it needs this bit at all.)
D, is the 'Cache Disable' bit. If set, the page will not be cached. Otherwise, it will be.
W, the controls 'Write-Through' abilities of the page. If the bit is set, write-through caching is enabled. If not, then write-back is enabled instead.
U, the user\supervisor bit, controls access to the page based on privilege level. If the bit is set, then the page may be accessed by all; if the bit is not set, however, only the supervisor can access it.
R, the read and write permissions flag, either makes the page only readable, that is, when it is not set, or makes the page both readable and writable, that is, being set.
P, or 'Presence', determines if the page is actually in physical memory at the moment. (eg. if a page only exists on the hard drive, it is not in physical memory.) If a page is called, but not present, a page fault will occur, and the OS should handle it. (See below.)
Page Table
In each page table, as it is, there are also 1024 entries. These are called page table entries, and are very similar to page directory entries.
Note: Only explanations of the bits unique to the page table are below.
The first item, is once again, a 4kb aligned physical address. Unlike previously, however, the address is not that of a page table, but instead a 4kb block of physical memory that is then mapped to that location in the page table and directory.
The Global, or 'G' above, flag, if set, prevents the TLB from updating the address in it's cache if CR3 is reset. Note, that the page global enable bit in CR4 must be set to enable this feature.
If the Dirty flag ('D') is set, then the page has been written to. This flag is not updated by the CPU, and once set will not unset itself.
The 'C' bit is 'D' bit above.
Example
Say I loaded my kernel to 0x100000. However, I want it mapped to 0xc0000000. After loading my kernel, I initiate paging, and set up the appropriate tables. (See Higher Half Kernel) After Identity Paging the first megabyte, I start to create my second table (ie. at entry #768 in my directory.) to map 0x100000 to 0xc0000000. My code could be like:
mov eax, 0x0
mov ebx, 0x100000
.fill_table:
mov ecx, ebx
or ecx, 3
mov [table_768+eax*4], ecx
add ebx, 4096
inc eax
cmp eax, 1024
je .end
jmp .fill_table
.end:
Enabling
Enabling paging is actually very simple. All that is needed is to load CR3 with the address of the page directory and to set the paging bit of CR0.
mov eax, [page_directory] mov cr3, eax mov eax, cr0 or eax, 0x80000000 mov cr0, eax
Usage
Due to the simplicity in the design of paging, it has many uses.
Virtual Address Spaces
In a paged system, each process may execute in its own 4gb area of memory, without any chance of effecting any other process's memory, or the kernel's.
Virtual Memory
Because paging allows for the dynamic handling of unallocated page tables, an OS can swap entire pages, not in current use, to the hard drive where they can wait until they are called. In the mean time, however, the physical memory that they were using can be used elsewhere. In this way, the OS can manipulate the system so that programs actually seem to have more RAM than there actually is.
More...
Page Faults
A page fault is an exception caused when a process is seeking to access an area of virtual memory that is not mapped to any physical memory.
Handling
Todo