Paging: Difference between revisions
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==MMU== |
==MMU== |
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Paging is achieved through the use of the [[MMU]]. The MMU is a unit that |
Paging is achieved through the use of the [[MMU]]. The MMU is a unit that transforms virtual addresses into physical addresses based on the current page table.This section focuses on the x86 MMU. |
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===Page Directory=== |
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The topmost paging structure is the page directory. It is essentially an array of page directory entries that take the following form. |
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Think of your RAM. It is probably several hundred megabytes of continuous non-volatile memory. Now, imagine that it is actually 4 gigabytes. This is what the MMU is paid to do with a little help from the kernel. |
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'''Note: With 5mb pages, bits 21 through 12 are Reserved!''' |
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In a 32bit Intel x86 CPU, there are 2 types of tables. There are the: |
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i* Page Directory |
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* Page Tables |
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[[Image:Page dir.png|frame|A Page Table Entry]] |
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Knowing this, there are some simple rules, if you will: |
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* There is only one page directory in use at any one time. |
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* Each structure consumes 4kb of space. |
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* Each entry in each structure is 4bytes in size. |
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The page table address field represents the physical address of the page table that managers the four megabytes at that point. Please note that it is very important that this address be 4kb aligned. This is needed, due to the fact that the last bits of the dword are overwritten by access bits and such. |
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The next valid flag, S, or 'Page Size', stores the page size for that specific entry. If the bit is set, then pages are 4mb in size. Otherwise, they are 4kb. |
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If you will recall, we know that the MMU is made to map x number of megabytes to 4 gigabytes. Considering this, we can now figure out how physical memory is mapped. |
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A, or 'Accessed' is used to discover whether a page has been read or written to. If it has, then the bit is set, otherwise, it is not. Note that, this bit will not be cleared by the CPU, so that burden falls on the OS. (ie. if it needs this bit at all.) |
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*page directory size = 4096 bytes |
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*page entry = 4 bytes |
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*number of directory entries = 4096/4 = 1024 |
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*number of table entries = directory entries = 1024 |
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*mapped RAM per directory entry (aka. a table) = 4gb/1024 = 4mb |
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*mapped RAM per table entry (aka. a page) = 4mb/1024 = 4kb. |
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D, is the 'Cache Disable' bit. If set, the page will not be cached. Otherwise, it will be. |
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There you have it. Each 'page' is then 4kb. |
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W, the controls 'Write-Through' abilities of the page. If the bit is set, write-through caching is enabled. If not, then write-back is enabled instead. |
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U, the user\supervisor bit, controls access to the page based on privilege level. If the bit is set, then the page may be accessed by all; if the bit is not set, however, only the supervisor can access it. |
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The structure of the above in computer speak is quite simple. Each entry is the address of it's child. If it's a directory entry, the entry consists of the table's address. Moreover, if it's a table's entry we're talking about, then it's the the address of the mapped physical memory. |
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R, the read and write permissions flag, either makes the page only readable, that is, when it is not set, or makes the page both readable and writable, that is, being set. |
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A short note, however, just to ruin your simplicity. Each entry described above also contains several flags. As this is a relaxed overview, I'll only list the three major ones here: |
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*Bits 31-12: 4kb aligned address of entry |
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*Bit 2: User\Supervisor |
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*Bit 1: Read\Write |
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*Bit 0: Presence Flag - While set, the MMU will assume that this page is currently in memory. |
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P, or 'Presence', determines if the page is actually in physical memory at the moment. (eg. if a page only exists on the hard drive, it is not in physical memory.) If a page is called, but not present, a page fault will occur, and the OS should handle it. (See below.) |
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Have you made the connection? Each page is 4kb, and each entry's address must be 4kb aligned! It's just clicking, isn't it? |
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===Page Table=== |
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Todo |
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====Example==== |
====Example==== |
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Revision as of 20:00, 15 November 2007
Overview
Paging is a memory scheme that breaks up memory in groups of pages that are constantly swapped between hard disk and computer. This allows for one to appear as though they have more memory than they actually do.
MMU
Paging is achieved through the use of the MMU. The MMU is a unit that transforms virtual addresses into physical addresses based on the current page table.This section focuses on the x86 MMU.
Page Directory
The topmost paging structure is the page directory. It is essentially an array of page directory entries that take the following form.
Note: With 5mb pages, bits 21 through 12 are Reserved!
The page table address field represents the physical address of the page table that managers the four megabytes at that point. Please note that it is very important that this address be 4kb aligned. This is needed, due to the fact that the last bits of the dword are overwritten by access bits and such.
The next valid flag, S, or 'Page Size', stores the page size for that specific entry. If the bit is set, then pages are 4mb in size. Otherwise, they are 4kb.
A, or 'Accessed' is used to discover whether a page has been read or written to. If it has, then the bit is set, otherwise, it is not. Note that, this bit will not be cleared by the CPU, so that burden falls on the OS. (ie. if it needs this bit at all.)
D, is the 'Cache Disable' bit. If set, the page will not be cached. Otherwise, it will be.
W, the controls 'Write-Through' abilities of the page. If the bit is set, write-through caching is enabled. If not, then write-back is enabled instead.
U, the user\supervisor bit, controls access to the page based on privilege level. If the bit is set, then the page may be accessed by all; if the bit is not set, however, only the supervisor can access it.
R, the read and write permissions flag, either makes the page only readable, that is, when it is not set, or makes the page both readable and writable, that is, being set.
P, or 'Presence', determines if the page is actually in physical memory at the moment. (eg. if a page only exists on the hard drive, it is not in physical memory.) If a page is called, but not present, a page fault will occur, and the OS should handle it. (See below.)
Page Table
Todo
Example
Say I loaded my kernel to 0x100000. However, I want it mapped to 0xc0000000. After loading my kernel, I initiate paging, and set up the appropriate tables. (See Higher Half Kernel) After Identity Paging the first megabyte, I start to create my second table (ie. at entry #768 in my directory.) to map 0x100000 to 0xc0000000. My code could be like:
mov eax, 0x0
mov ebx, 0x100000
.fill_table:
mov ecx, ebx
or ecx, 3
mov [table_768+eax*4], ecx
add ebx, 4096
inc eax
cmp eax, 1024
je .end
jmp .fill_table
.end:
Enabling
Enabling paging is actually very simple. All that is needed is to load CR3 with the address of the page directory and to set the paging bit of CR0.
mov eax, [page_directory] mov cr3, eax mov eax, cr0 or eax, 0x80000000 mov cr0, eax
Usage
Todo
Page Faults
A page fault is an exception caused when a process is seeking to access an area of virtual memory that is not mapped to any physical memory.
Handling
Todo