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Added a relaxed MMU\Page Structure overview |
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==MMU== |
==MMU== |
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Paging is achieved through the use of the [[MMU]]. |
Paging is achieved through the use of the [[MMU]]. The MMU is a unit that wonderfully transforms virtual addresses into physical addresses based on the current paging table. |
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===Relaxed Technical Overview=== |
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Think of your RAM. It is probably several hundred megabytes of continuous non-volatile memory. Now, imagine that it is actually 4 gigabytes. This is what the MMU is paid to do with a little help from the kernel. |
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In a 32bit Intel x86 CPU, there are 2 types of tables. There are the: |
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i* Page Directory |
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* Page Tables |
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Knowing this, there are some simple rules, if you will: |
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* There is only one page directory in use at any one time. |
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* Each structure consumes 4kb of space. |
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* Each entry in each structure is 4bytes in size. |
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If you will recall, we know that the MMU is made to map x number of megabytes to 4 gigabytes. Considering this, we can now figure out how physical memory is mapped. |
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*page directory size = 4096 bytes |
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*page entry = 4 bytes |
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*number of directory entries = 4096/4 = 1024 |
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*number of table entries = directory entries = 1024 |
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*mapped RAM per directory entry (aka. a table) = 4gb/1024 = 4mb |
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*mapped RAM per table entry (aka. a page) = 4mb/1024 = 4kb. |
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There you have it. Each 'page' is then 4kb. |
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The structure of the above in computer speak is quite simple. Each entry is the address of it's child. If it's a directory entry, the entry consists of the table's address. Moreover, if it's a table's entry we're talking about, then it's the the address of the mapped physical memory. |
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A short note, however, just to ruin your simplicity. Each entry described above also contains 3 flags on the least significant bits. The full layout is as follows: |
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*Bits 31-3: 4kb aligned address of entry |
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*Bit 2: Modified flag - Pages with this set must be copied to disk before deletion. |
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*Bit 1: Used Flag - While set, the MMU assumes that this page is actively mapped to some physical address. |
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*Bit 0: Presence Flag - While set, the MMU will assume that this page is currently in memory. |
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Have you made the connection? Each page is 4kb, and each entry's address must be 4kb aligned! It's just clicking, isn't it? |
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====Example==== |
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Say I loaded my kernel to 0x100000. However, I want it mapped to 0xc0000000. After loading my kernel, I initiate paging, and set up the appropriate tables. (See [[Higher Half Kernel]]) After [[Identity Paging]] the first megabyte, I start to create my second table (ie. at entry #768 in my directory.) to map 0x100000 to 0xc0000000. My code could be like: |
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mov eax, 0x0 |
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mov ebx, 0x100000 |
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.fill_table: |
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mov ecx, ebx |
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or ecx, 3 |
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mov [table_768+eax*4], ecx |
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add ebx, 4096 |
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inc eax |
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cmp eax, 1024 |
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je .end |
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jmp .fill_table |
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.end: |
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==Enabling== |
==Enabling== |