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=== Page Table === |
=== Page Table === |
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[[Image:Page table.png|frame|A Page Table Entry]] |
[[Image:Page table entry.png|frame|A Page Table Entry]] |
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In each page table, as it is, there are also 1024 entries. These are called page table entries, and are '''very''' similar to page directory entries. |
In each page table, as it is, there are also 1024 entries. These are called page table entries, and are '''very''' similar to page directory entries. |
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⚫ | The first item, is once again, a 4-KiB aligned physical address. Unlike previously, however, the address is not that of a page table, but instead a 4 KiB block of physical memory that is then mapped to that location in the page table and directory. Note that the PAT bit is bit 7 instead of bit 12 as in the 4 MiB PDE. |
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''Note: Only explanations of the bits unique to the page table are below. |
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⚫ | |||
* C, or '''C'''ached, is the 'D' bit from the previous table |
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* G, or the '''G'''lobal, flag, if set, prevents the [[TLB]] from updating the address in its cache if CR3 is reset. Note, that the page global enable bit in CR4 must be set to enable this feature. |
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* D, or the '''D'''irty flag, if set, indicates that page has been written to. This flag is not updated by the CPU, and once set will not unset itself. |
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* 0, if [https://en.wikipedia.org/wiki/Page_attribute_table PAT] is supported, shall indicate the memory type. Otherwise, it must be 0. |
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=== Example === |
=== Example === |