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The page table address field represents the physical address of the page table that managers the four megabytes at that point. Please note that it is very important that this address be 4 KiB aligned. This is needed, due to the fact that the last bits of the dword are overwritten by access bits and such. |
The page table address field represents the physical address of the page table that managers the four megabytes at that point. Please note that it is very important that this address be 4 KiB aligned. This is needed, due to the fact that the last bits of the dword are overwritten by access bits and such. |
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* S, or 'Page '''S'''ize' stores the page size for that specific entry. If the bit is set, then pages are 4 MiB in size. Otherwise, they are 4 KiB. |
* S, or 'Page '''S'''ize' stores the page size for that specific entry. If the bit is set, then pages are 4 MiB in size. Otherwise, they are 4 KiB. Please note that for 4 MiB pages PSE have to be enabled. |
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* A, or ''''A'''ccessed' is used to discover whether a page has been read or written to. If it has, then the bit is set, otherwise, it is not. Note that, this bit will not be cleared by the CPU, so that burden falls on the OS (if it needs this bit at all). |
* A, or ''''A'''ccessed' is used to discover whether a page has been read or written to. If it has, then the bit is set, otherwise, it is not. Note that, this bit will not be cleared by the CPU, so that burden falls on the OS (if it needs this bit at all). |
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* D, is the 'Cache '''D'''isable' bit. If the bit is set, the page will not be cached. Otherwise, it will be. |
* D, is the 'Cache '''D'''isable' bit. If the bit is set, the page will not be cached. Otherwise, it will be. |
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mov eax, cr0 |
mov eax, cr0 |
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bts eax, 31 |
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mov cr0, eax |
mov cr0, eax |
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To enable PSE (4 MiB pages) the following code is required. |
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mov eax, cr4 |
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bts eax, 4 |
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mov cr4, eax |
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==Usage== |
==Usage== |
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