PCI IDE Controller: Difference between revisions

To initialise the IDE driver, we call ide_initialise:

void ide_initialize(unsigned int BAR0, unsigned int BAR1, unsigned int BAR2, unsigned int BAR3,

unsigned int BAR4) {

If you only want to support the parallel IDE, you can use these parameters:

ide_initialize(0x1F0, 0x3F6, 0x170, 0x376, 0x000);

We can assume that BAR4 is 0x0 because we are not going to use it yet.

The Command/Status Port returns a bit mask referring to the status of a channel when read.

#define ATA_SR_BSY 0x80 // Busy

#define ATA_SR_DRDY 0x40 // Drive ready

#define ATA_SR_IDX 0x02 // Index

#define ATA_SR_ERR 0x01 // Error

=== Errors ===

The Features/Error Port, which returns the most recent error upon read, has these possible bit masks

#define ATA_ER_BBK 0x80 // Bad block

#define ATA_ER_UNC 0x40 // Uncorrectable data

#define ATA_ER_TK0NF 0x02 // Track 0 not found

#define ATA_ER_AMNF 0x01 // No address mark

=== Commands ===

When you write to the Command/Status port, you are executing one of the commands below.

#define ATA_CMD_READ_PIO 0x20

#define ATA_CMD_READ_PIO_EXT 0x24

#define ATA_CMD_IDENTIFY_PACKET 0xA1

#define ATA_CMD_IDENTIFY 0xEC

The commands below are for ATAPI devices, which will be understood soon.

#define ATAPI_CMD_READ 0xA8

#define ATAPI_CMD_EJECT 0x1B

ATA_CMD_IDENTIFY_PACKET and ATA_CMD_IDENTIFY return a buffer of 512 bytes called the identification space; the following definitions are used to read information from the identification space.

#define ATA_IDENT_DEVICETYPE 0

#define ATA_IDENT_CYLINDERS 2

#define ATA_IDENT_COMMANDSETS 164

#define ATA_IDENT_MAX_LBA_EXT 200

When you select a drive, you should specify the interface type and whether it is the master or slave:

#define IDE_ATA 0x00

#define IDE_ATAPI 0x01

#define ATA_MASTER 0x00

#define ATA_SLAVE 0x01

Task File is a range of 8 ports which are offsets from BAR0 (primary channel) and/or BAR2 (secondary channel). To exemplify:

* BAR0 + 1 is second port.

* BAR0 + 2 is the third

#define ATA_REG_DATA 0x00

#define ATA_REG_ERROR 0x01

#define ATA_REG_ALTSTATUS 0x0C

#define ATA_REG_DEVADDRESS 0x0D

The ALTSTATUS/CONTROL port returns the alternate status when read and controls a channel when written to.

The map above is the same with the secondary channel, but it uses BAR2 and BAR3 instead of BAR0 and BAR1.

// Channels:

#define ATA_PRIMARY 0x00

#define ATA_READ 0x00

#define ATA_WRITE 0x01

We have defined everything needed by the driver, now lets move to an important part. We said that

So we can make this global structure:

struct IDEChannelRegisters {

unsigned short base; // I/O Base.

unsigned char nIEN; // nIEN (No Interrupt);

} channels[2];

We also need a buffer to read the identification space into, we need a variable that indicates if an irq is invoked or not, and finally we need an array of 6 words [12 bytes] for ATAPI Drives:

unsigned char ide_buf[2048] = {0};

volatile unsigned static char ide_irq_invoked = 0;

unsigned static char atapi_packet[12] = {0xA8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};

We said the the IDE can contain up to 4 drives:

struct ide_device {

unsigned char Reserved; // 0 (Empty) or 1 (This Drive really exists).

unsigned char Model[41]; // Model in string.

} ide_devices[4];

When we read a register in a channel, like STATUS Register, it is easy to execute:

If there is an error, we have a function which prints errors on screen:

unsigned char ide_print_error(unsigned int drive, unsigned char err) {

if (err == 0)

return err;

}

Now let's return to the initialization function:

void ide_initialize(unsigned int BAR0, unsigned int BAR1, unsigned int BAR2, unsigned int BAR3,

unsigned int BAR4) {

channels[ATA_PRIMARY ].bmide = (BAR4 & 0xFFFFFFFC) + 0; // Bus Master IDE

channels[ATA_SECONDARY].bmide = (BAR4 & 0xFFFFFFFC) + 8; // Bus Master IDE

Then we should disable IRQs in both channels by setting bit 1 (nIEN) in the Control port:

// 2- Disable IRQs:

ide_write(ATA_PRIMARY , ATA_REG_CONTROL, 2);

ide_write(ATA_SECONDARY, ATA_REG_CONTROL, 2);

Now we need to check for drives which could be connected to each channel. We will select the master drive of each channel, and send the ATA_IDENTIFY command (which is supported by ATA Drives). If there's no error, there are values returned in registers which determine the type of Drive; if no drive is present, there will be strange values.

We can conclude also this table:

/* ATA/ATAPI Read/Write Modes:

* ++++++++++++++++++++++++++++++++

* - Polling Status (+) // Suitable for Singletasking

*/

There is something needed to be expressed here, I have told before that Task-File is like that:

Lets go into the code:

unsigned char ide_ata_access(unsigned char direction, unsigned char drive, unsigned int lba,

unsigned char numsects, unsigned short selector, unsigned int edi) {

This function reads/writes sectors from ATA-Drive. If direction is 0 we are reading, else we are writing.

* edi is the offset in that segment. (the memory address for the data buffer)

unsigned char lba_mode /* 0: CHS, 1:LBA28, 2: LBA48 */, dma /* 0: No DMA, 1: DMA */, cmd;

unsigned char lba_io[6];

unsigned short cyl, i;

unsigned char head, sect, err;

We don't need IRQs, so we should disable it to prevent problems from happening. We said before that if bit 1 of the Control Register (which is called nIEN bit), is set, no IRQs will be invoked from any drives on this channel, either master or slave.

ide_write(channel, ATA_REG_CONTROL, channels[channel].nIEN = (ide_irq_invoked = 0x0) + 0x02);

Now lets read the parameters:

// (I) Select one from LBA28, LBA48 or CHS;

if (lba >= 0x10000000) { // Sure Drive should support LBA in this case, or you are

head = (lba + 1 - sect) % (16 * 63) / (63); // Head number is written to HDDEVSEL lower 4-bits.

}

Now we are going to choose the way of reading the buffer [PIO or DMA]:

// (II) See if drive supports DMA or not;

dma = 0; // We don't support DMA

Lets poll the Status port while the channel is busy:

// (III) Wait if the drive is busy;

while (ide_read(channel, ATA_REG_STATUS) & ATA_SR_BSY){

} // Wait if busy.

The HDDDEVSEL register now looks like this:

Let's write the parameters to registers:

// (V) Write Parameters;

if (lba_mode == 2) {

ide_write(channel, ATA_REG_LBA1, lba_io[1]);

ide_write(channel, ATA_REG_LBA2, lba_io[2]);

If you are using LBA48 and want to write to the LBA0 and LBA3 registers, you should write LBA3 to Register 3, then write LBA0 to Register 3. ide_write function makes it quite simple, refer to the function and you will fully understand the code.

Now, we have a great set of commands described in ATA/ATAPI-8 Specification, we should choose the suitable command to execute:

// (VI) Select the command and send it;

// Routine that is followed:

// If (!DMA & LBA28) DO_PIO_LBA;

// If (!DMA & !LBA#) DO_PIO_CHS;

There isn't a command for doing CHS with DMA.

if (lba_mode == 0 && dma == 0 && direction == 0) cmd = ATA_CMD_READ_PIO;

if (lba_mode == 1 && dma == 0 && direction == 0) cmd = ATA_CMD_READ_PIO;

if (lba_mode == 2 && dma == 1 && direction == 1) cmd = ATA_CMD_WRITE_DMA_EXT;

ide_write(channel, ATA_REG_COMMAND, cmd); // Send the Command.

This ATA_CMD_READ_PIO command is used for reading in LBA28 or CHS, and the IDE controller refers to bit 6 of the HDDEVSEL register to find out the mode of reading (LBA or CHS).

Notice also that ATAPI drives always use IRQs and you can't disable them. We should create a function that waits for an IRQ:

void ide_wait_irq() {

while (!ide_irq_invoked)

ide_irq_invoked = 0;

}

When an IRQ happens, the following function should be executed by ISR:

void ide_irq() {

ide_irq_invoked = 1;

}

ide_wait_irq will go into a while loop, which waits for the variable ide_irq_invoked to be set, then clears it.

unsigned char ide_atapi_read(unsigned char drive, unsigned int lba, unsigned char numsects,

unsigned short selector, unsigned int edi) {

* drive is the drive number, which is from 0 to 3.

Let's read the parameters of the drive:

unsigned int channel = ide_devices[drive].Channel;

unsigned int slavebit = ide_devices[drive].Drive;

unsigned char err;

int i;

We need IRQs:

// Enable IRQs:

ide_write(channel, ATA_REG_CONTROL, channels[channel].nIEN = ide_irq_invoked = 0x0);

Let's setup the SCSI Packet, which is 6 words (12 bytes) long:

// (I): Setup SCSI Packet:

// ------------------------------------------------------------------

atapi_packet[10] = 0x0;

atapi_packet[11] = 0x0;

Now we should select the drive:

</source>

// (IV): Inform the Controller that we use PIO mode:

// ------------------------------------------------------------------

ide_write(channel, ATA_REG_FEATURES, 0); // PIO mode.

Tell the controller the size of the buffer

// (V): Tell the Controller the size of buffer:

// ------------------------------------------------------------------

ide_write(channel, ATA_REG_LBA1, (words * 2) & 0xFF); // Lower Byte of Sector Size.

ide_write(channel, ATA_REG_LBA2, (words * 2) >> 8); // Upper Byte of Sector Size.

Now that we want to send the packet, we should first send the command "Packet":

// (VI): Send the Packet Command:

// ------------------------------------------------------------------

// ------------------------------------------------------------------

asm("rep outsw" : : "c"(6), "d"(bus), "S"(atapi_packet)); // Send Packet Data

Here we cannot poll. We should wait for an IRQ, then read the sectors. These two operations should be repeated for each sector.

Now we should wait for an IRQ and poll until the Busy and DRQ bits are clear:

// (X): Waiting for an IRQ:

// ------------------------------------------------------------------

return 0; // Easy, ... Isn't it?

}

== Reading from an ATA/ATAPI Drive ==

== Writing to an ATA drive ==

void ide_write_sectors(unsigned char drive, unsigned char numsects, unsigned int lba,

unsigned short es, unsigned int edi) {

}

}

== Ejecting an ATAPI Drive ==