PCI: Difference between revisions
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→Enabling MSI-X: Clean up section
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! register !! offset !! bits 31-24 !! bits 23-16 !! bits 15-8 !! bits 7-3 !! bits 2-0
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| colspan="2" | Message Control
| Next
| colspan="2" | Capability ID = 11
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| colspan="4" | Table Offset
| colspan="1" | BIR
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| colspan="4" | Pending Bit Offset
| colspan="1" | Pending Bit BIR
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Unlike MSI, MSI-X supports 2048 interrupts. This is achieved by maintaining a table of interrupts in the PCI device's address space. The wording of the PCI 3.0
'''BIR''' specifies which BAR is used for the Message Table. This may be a 64
'''Table Offset''' is an offset into that BAR where the Message Table lives. Note that it is 8
The format of Message Control is as follows:
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! Bit 15 !! Bit 14 !!
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| Enable
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'''Table Size''' is N - 1 encoded, and is the number of entries in the MSI-X table. This field is Read-Only.
Now you have all the information you need to find the MSI-X table:
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!
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| Vector Control (0)
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| Vector Control (N - 1)
| Message Data (N - 1)
| Message Address High (N - 1)
| Message Address Low (N - 1)
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!
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| Reserved
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Note that '''Message Address''' is is
Message Address and Data are as they were for MSI - architecture specific. However, unlike with MSI, you can specify independent vectors for all the interrupts, only limited by having the same upper 32
== Multifunction Devices ==
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