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=== Enabling MSI ===
=== Enabling MSI ===
First, check that the device has a pointer to the capabilities list (Status register bit 4 set to 1).
First, check that the device has a pointer to the capabilities list (status register bit 4 set to 1).
Then, traverse the capabilities list. The low 8 bits of a capability register are the ID - 0x05 for MSI. The next 8 bits are the offset (in PCI configuration space) of the next capability.
Then, traverse the capabilities list. The low 8 bits of a capability register are the ID - 0x5 for MSI. The next 8 bits are the offset (in [[#Configuration Space|PCI Configuration Space]]) of the next capability.


The MSI capability is as folows:
The MSI capability is as follows:
{| {{wikitable}}
{| {{wikitable}}
|-
|-
! register !! offset !! bits 31-24 !! bits 23-16 !! bits 15-8 !! bits 7-0
! Register !! Offset !! Bits 31-24 !! Bits 23-16 !! Bits 15-8 !! Bits 7-0
|-
|-
| cap+00
| Cap + 0x0
| cap+00
| Cap + 0x0
| colspan="2" | Message Control
| colspan="2" | Message Control
| Next ptr || Capability ID = 05
| Next pointer || Capability ID = 05
|-
|-
| cap+01
| Cap + 0x1
| cap+04
| Cap + 0x4
| colspan="4" | Message Address [Low]
| colspan="4" | Message Address [Low]
|-
|-
| cap+02
| Cap + 0x2
| cap+08
| Cap + 0x8
| colspan="4" | [Message Address High]
| colspan="4" | [Message Address High]
|-
|-
| cap+02/03
| Cap + 0x2/0x3
| cap+08/0C
| Cap + 0x8/0xC
| colspan="2" | Reserved
| colspan="2" | Reserved
| colspan="2" | Message Data
| colspan="2" | Message Data
|-
|-
| cap+04
| Cap + 0x4
| cap+10
| Cap + 0x10
| colspan="4" | [Mask]
| colspan="4" | [Mask]
|-
|-
| cap+05
| Cap + 0x5
| cap+14
| Cap + 0x14
| colspan="4" | [Pending]
| colspan="4" | [Pending]
|}
|}
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{| {{wikitable}}
{| {{wikitable}}
|-
|-
! Bit 15-9 !! Bit 8 !! Bit 7 !! Bit 6-4 !! Bit 3-1 !! Bit 0
! Bits 15-9 !! Bit 8 !! Bit 7 !! Bits 6-4 !! Bits 3-1 !! Bit 0
|-
|-
| Reserved
| Reserved
| Per-vector masking
| Per-vector masking
| 64 bit
| 64-bit
| Multiple Message Enable
| Multiple Message Enable
| Multiple Message Capable
| Multiple Message Capable
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The message address/data is architecture specific. On x86(-64), it is as follows:
The message address/data is architecture specific. On x86(-64), it is as follows:
<source lang="c">
<source lang="c">
paddr_t arch_msi_address(uint64_t* data, size_t vector, uint32_t processor, uint8_t edgetrigger, uint8_t deassert)
uint64_t arch_msi_address(uint64_t *data, size_t vector, uint32_t processor, uint8_t edgetrigger, uint8_t deassert) {
{
*data = (vector & 0xFF) | (edgetrigger == 1 ? 0 : (1 << 15)) | (deassert == 1 ? 0 : (1 << 14));
*data = (vector & 0xFF) | (edgetrigger == 1 ? 0 : (1 << 15)) | (deassert == 1 ? 0 : (1 << 14));
return (0xFEE00000 | (processor << 12));
return (0xFEE00000 | (processor << 12));
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'''Interrupt masking'''
'''Interrupt masking'''


If capable, you can mask individual messages by setting the corresponding bit (1<<x), in the mask register.
If capable, you can mask individual messages by setting the corresponding bit (1 << n), in the mask register.


If a message is pending, then the corresponding bit in the pending register is set.
If a message is pending, then the corresponding bit in the pending register is set.


Note that the PCI specification doesn't specify the location of these registers if the message address is 32 bit. This is because a function that supports masking is required to implement 64 bit addressing!
Note that the PCI specification doesn't specify the location of these registers if the message address is 32-bit. This is because a function that supports masking is required to implement 64-bit addressing!


=== Enabling MSI-X ===
=== Enabling MSI-X ===
Retrieved from "https://osdev.wiki/wiki/PCI"