Native Intel graphics: Difference between revisions

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===Architecture overview===
===Architecture overview===


G45 chips appear as devices on the PCI bus. They are identified a vendor ID of 0x8086 and a model-specific device ID. The PCI configuration space is used to access two BARs: The first BAR points to a MMIO region that contains all registers of the card. The second BAR allows access to the graphics memory.
G45 chips appear as devices on the PCI bus. They are identified a vendor ID of 0x8086 and a model-specific device ID. The PCI configuration space is used to access two BARs: The BAR 0 points to a MMIO region that contains all registers of the card. BAR 2 allows access to the graphics memory.


The chip supports two independent graphics pipelines. Each pipeline is made of the following:
The chip supports two independent graphics pipelines. Each pipeline is made of the following:
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