Native Intel graphics: Difference between revisions

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=Introduction=
==Introduction==


Intel has produced a number of graphics chips that are integrated into their chipsets and processors.
Intel has produced a number of graphics chips that are integrated into their chipsets and processors.
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2D and 3D graphics operations via shader programs.
2D and 3D graphics operations via shader programs.


==Prerequisites==
===Prerequisites===


Before trying to implement a native driver for your OS make sure to understand the basics first.
Before trying to implement a native driver for your OS make sure to understand the basics first.
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* You need to be able to access [[PCI]] configuration space and find MMIO regions that are determined by BARs.
* You need to be able to access [[PCI]] configuration space and find MMIO regions that are determined by BARs.


=Getting EDID via DDC=
==Getting EDID via DDC==


TODO
TODO


=Generation 4 GMA desktop chips (aka Intel G45)=
==Generation 4 GMA desktop chips (aka Intel G45)==


The G45 is a PCI-Express based graphics chip that was introduced by Intel in 2008.
The G45 is a PCI-Express based graphics chip that was introduced by Intel in 2008.


==Architecture overview==
===Architecture overview===


G45 chips appear as devices on the PCI bus. They are identified a vendor ID of 0x8086 and a model-specific device ID. The PCI configuration space is used to access two BARs: The first BAR points to a MMIO region that contains all registers of the card. The second BAR allows access to the graphics memory.
G45 chips appear as devices on the PCI bus. They are identified a vendor ID of 0x8086 and a model-specific device ID. The PCI configuration space is used to access two BARs: The first BAR points to a MMIO region that contains all registers of the card. The second BAR allows access to the graphics memory.
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Both pipelines share a set of connectors that are used to attach monitors to the card.
Both pipelines share a set of connectors that are used to attach monitors to the card.


==Mode setting==
===Mode setting===


Mode setting proceeds in two phases: First the display hardware needs to be deactivated. After that it can be reprogrammed and enabled again in another mode.
Mode setting proceeds in two phases: First the display hardware needs to be deactivated. After that it can be reprogrammed and enabled again in another mode.
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* Enable the output connectors.
* Enable the output connectors.


===Programming the DPLL===
====Programming the DPLL====


Before a display pipe can be enabled its DPLL has to be programmed to generate a suitable pixel clock for the desired graphics mode.
Before a display pipe can be enabled its DPLL has to be programmed to generate a suitable pixel clock for the desired graphics mode.
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* Compute N, M1, M2, P1 and P2 from the DPLL clock. This can be done by iterating over all possible N, M1, M2, P1 and P2 values and checking if each combination falls into the allowed limits.
* Compute N, M1, M2, P1 and P2 from the DPLL clock. This can be done by iterating over all possible N, M1, M2, P1 and P2 values and checking if each combination falls into the allowed limits.


===Programming the display pipes===
====Programming the display pipes====


===Handling planes===
====Handling planes====


===Enabling and disabling connectors===
====Enabling and disabling connectors====