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NVMe: Difference between revisions
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== Overview ==
* NVMe controllers can be found as [[PCI]] devices with class code 1 and subclass code 8.
* Its registers are accessible through BAR 0 (it should be 64-bit memory IO).
* The controller processes commands submitted to it from "submission queues". The driver prepares commands in the queue's circular buffer in memory, and then updates the tail pointer register for the queue.
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