Model Specific Registers: Difference between revisions
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===Other access to MSRs=== |
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As <code>rdmsr</code> and <code>wrmsr</code> are priveleged instructions, there are a few MSRs which are deemed safe for non-priveleged access. For example, the <code>rdtsc</code> instruction is a non priveleged instruction which will read the timestamp counter which is actually situated in an MSR. |
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==See Also== |
==See Also== |
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Revision as of 22:43, 19 April 2011
Processors from P6 family (including Pentium PRO, Pentium 3 & 4) have a collection of registers that allows configuration of various things such as memory type-range, sysenter/sysexit, local APIC, etc.
Accessing Model Specific Registers
Each MSR has a single 32-bit identification number that will be given to RDMSR or WRMSR assembly instructions to operate it. MSRs are 64-bit wide. The presence of MSRs on your processor is indicated by CPUID.01h:EDX[bit 5].
bool cpuHasMSR()
{
uint32_t a, d;
cpuid(1, &a, &d);
return d & CPUID_FLAG_MSR;
}
void cpuGetMSR(uint32_t msr, uint32_t *lo, uint32_t *hi)
{
asm volatile("rdmsr":"=a"(*lo),"=d"(*hi):"c"(msr));
}
void cpuSetMSR(uint32_t msr, uint32_t lo, uint32_t hi)
{
asm volatile("wrmsr"::"a"(lo),"d"(hi),"c"(msr));
}
Other access to MSRs
As rdmsr and wrmsr are priveleged instructions, there are a few MSRs which are deemed safe for non-priveleged access. For example, the rdtsc instruction is a non priveleged instruction which will read the timestamp counter which is actually situated in an MSR.