Model Specific Registers: Difference between revisions
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(C is not Pascal, nor assembly. Also, some spaces.) |
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<source lang="c"> |
<source lang="c"> |
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bool cpuHasMSR() |
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{ |
{ |
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uint32_t a, d; |
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cpuid(1,&a,&d); |
cpuid(1, &a, &d); |
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return d&CPUID_FLAG_MSR; |
return d & CPUID_FLAG_MSR; |
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} |
} |
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void cpuGetMSR( |
void cpuGetMSR(uint32_t msr, uint32_t *lo, uint32_t *hi) |
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{ |
{ |
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asm volatile("rdmsr":"=a"(*lo),"=d"(*hi):"c"(msr)); |
asm volatile("rdmsr":"=a"(*lo),"=d"(*hi):"c"(msr)); |
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} |
} |
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void cpuSetMSR( |
void cpuSetMSR(uint32_t msr, uint32_t lo, uint32_t hi) |
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{ |
{ |
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asm volatile("wrmsr"::"a"(lo),"d"(hi),"c"(msr)); |
asm volatile("wrmsr"::"a"(lo),"d"(hi),"c"(msr)); |
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Revision as of 14:53, 19 April 2011
Processors from P6 family (including Pentium PRO, Pentium 3 & 4) have a collection of registers that allows configuration of various things such as memory type-range, sysenter/sysexit, local APIC, etc.
Accessing Model Specific Registers
Each MSR has a single 32-bit identification number that will be given to RDMSR or WRMSR assembly instructions to operate it. MSRs are 64-bit wide. The presence of MSRs on your processor is indicated by CPUID.01h:EDX[bit 5].
bool cpuHasMSR()
{
uint32_t a, d;
cpuid(1, &a, &d);
return d & CPUID_FLAG_MSR;
}
void cpuGetMSR(uint32_t msr, uint32_t *lo, uint32_t *hi)
{
asm volatile("rdmsr":"=a"(*lo),"=d"(*hi):"c"(msr));
}
void cpuSetMSR(uint32_t msr, uint32_t lo, uint32_t hi)
{
asm volatile("wrmsr"::"a"(lo),"d"(hi),"c"(msr));
}