Model Specific Registers: Difference between revisions
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== Accessing Model Specific Registers == |
== Accessing Model Specific Registers == |
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Each MSR has a single 32-bit identification number that will be given to RDMSR or WRMSR assembly instructions to operate it. MSRs are 64-bit wide. The presence of MSRs on your processor is indicated by bit 5 |
Each MSR has a single 32-bit identification number that will be given to RDMSR or WRMSR assembly instructions to operate it. MSRs are 64-bit wide. The presence of MSRs on your processor is indicated by [[CPUID]].01h:EDX[bit 5]. |
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<source lang="c"> |
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<pre> |
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boolean cpuHasMSR() |
boolean cpuHasMSR() |
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{ |
{ |
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asm volatile("wrmsr"::"a"(lo),"d"(hi),"c"(msr)); |
asm volatile("wrmsr"::"a"(lo),"d"(hi),"c"(msr)); |
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} |
} |
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</ |
</source> |
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==See Also== |
==See Also== |
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Revision as of 18:12, 19 January 2011
Processors from P6 family (including Pentium PRO, Pentium 3 & 4) have a collection of registers that allows configuration of various things such as memory type-range, sysenter/sysexit, local APIC, etc.
Accessing Model Specific Registers
Each MSR has a single 32-bit identification number that will be given to RDMSR or WRMSR assembly instructions to operate it. MSRs are 64-bit wide. The presence of MSRs on your processor is indicated by CPUID.01h:EDX[bit 5].
boolean cpuHasMSR()
{
dword a,d;
cpuid(1,&a,&d);
return d&CPUID_FLAG_MSR;
}
void cpuGetMSR(dword msr, dword *lo, dword *hi)
{
asm volatile("rdmsr":"=a"(*lo),"=d"(*hi):"c"(msr));
}
void cpuSetMSR(dword msr, dword lo, dword hi)
{
asm volatile("wrmsr"::"a"(lo),"d"(hi),"c"(msr));
}