MTRR: Difference between revisions

From OSDev.wiki
Jump to navigation Jump to search
[unchecked revision][unchecked revision]
Content added Content deleted
(Initial text (MSR mappings))
 
m (Added category)
Line 21: Line 21:
** IA32_MTRR_FIX4K_F0000, in MSR[26E] - 8 regions of 4 KB each (32 KB total)
** IA32_MTRR_FIX4K_F0000, in MSR[26E] - 8 regions of 4 KB each (32 KB total)
** IA32_MTRR_FIX4K_F8000, in MSR[26F] - 8 regions of 4 KB each (32 KB total)
** IA32_MTRR_FIX4K_F8000, in MSR[26F] - 8 regions of 4 KB each (32 KB total)

[[Category:Stubs]]

Revision as of 15:32, 11 January 2010

Memory Type Range Registers

History

The MTRR were introduced in the Intel Pentium Pro (P6) processor. They were intended to extend and enhance the memory type information provided by page tables (i.e. the write-through and cache disable bits).

Implementation Details

  • Register IA32_MTRRCAP is MSR[FE]
  • There are 8 variable ranges, split into a base and mask:
    • IA32_MTRR_PHYSBASE{x=0..7}, in MSR[200+x*2]
    • IA32_MTRR_PHYSMASK{x=0..7}, in MSR[201+x*2]
  • There are 88 fixed ranges, covering the bottom 1MB
    • IA32_MTRR_FIX64K_00000, in MSR[250] - 8 regions of 64 KB each (512 KB total)
    • IA32_MTRR_FIX16K_80000, in MSR[258] - 8 regions of 16 KB each (128 KB total)
    • IA32_MTRR_FIX16K_A0000, in MSR[259] - 8 regions of 16 KB each (128 KB total)
    • IA32_MTRR_FIX4K_C0000, in MSR[268] - 8 regions of 4 KB each (32 KB total)
    • IA32_MTRR_FIX4K_C8000, in MSR[269] - 8 regions of 4 KB each (32 KB total)
    • IA32_MTRR_FIX4K_D0000, in MSR[26A] - 8 regions of 4 KB each (32 KB total)
    • IA32_MTRR_FIX4K_D8000, in MSR[26B] - 8 regions of 4 KB each (32 KB total)
    • IA32_MTRR_FIX4K_E0000, in MSR[26C] - 8 regions of 4 KB each (32 KB total)
    • IA32_MTRR_FIX4K_E8000, in MSR[26D] - 8 regions of 4 KB each (32 KB total)
    • IA32_MTRR_FIX4K_F0000, in MSR[26E] - 8 regions of 4 KB each (32 KB total)
    • IA32_MTRR_FIX4K_F8000, in MSR[26F] - 8 regions of 4 KB each (32 KB total)