MMX: Difference between revisions
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=Overview= |
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MMX is a SIMD technology (single instruction, multiple data) introduced by Intel with |
MMX is a SIMD technology (single instruction, multiple data) introduced by Intel on January 8, 1997 with their P5 "Pentium" processor line named "Pentium with MMX Technology". It has been superseded by [[SSE]] and now [[AVX]]. |
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==Technical Details== |
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MMX is accessed using 8 CPU registers (MM0 to MM7). Each register is 64 bits wide and can be used to hold 64-bit integers or multiple smaller integers packed. One instruction can be applied to two 32-bit integers, four 16-bit integers, or 8 8-bit integers at once. |
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==Detection== |
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*[[SSE]] |
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*[[FPU]] |
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=MMX in 2021= |
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MMX is now an old technology that was left in the past in favour of the new technologies [[SSE]] and [[AVX]]. |
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Latest revision as of 06:39, 12 July 2021
| Real numbers, coprocessors and vector units |
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| Technical |
| X86 implementations |
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Overview
MMX is a SIMD technology (single instruction, multiple data) introduced by Intel on January 8, 1997 with their P5 "Pentium" processor line named "Pentium with MMX Technology". It has been superseded by SSE and now AVX.
Technical Details
MMX is accessed using 8 CPU registers (MM0 to MM7). Each register is 64 bits wide and can be used to hold 64-bit integers or multiple smaller integers packed. One instruction can be applied to two 32-bit integers, four 16-bit integers, or 8 8-bit integers at once.
Detection
The bit for MMX can be found on CPUID page 1, in EDX bit 23.
MMX in 2021
MMX is now an old technology that was left in the past in favour of the new technologies SSE and AVX.