Low Pin Count: Difference between revisions
Jump to navigation
Jump to search
[unchecked revision] | [unchecked revision] |
Content added Content deleted
No edit summary |
No edit summary |
||
Line 4: | Line 4: | ||
== See Also == |
== See Also == |
||
*[ |
*[https://www.intel.com/content/dam/www/program/design/us/en/documents/low-pin-count-interface-specification.pdf Intel Low Pin Count Specification] |
||
*[https://en.wikipedia.org/wiki/Low_Pin_Count Low Pin Count on Wikipedia] |
*[https://en.wikipedia.org/wiki/Low_Pin_Count Low Pin Count on Wikipedia] |
||
[[Category:Buses]] |
[[Category:Buses]] |
Latest revision as of 20:32, 9 July 2023
This page is a stub.
You can help the wiki by accurately adding more contents to it.
The Low Pin Count bus, (or LPC bus,) is used to connect low bandwidth devices to the CPU such as serial & parallel ports, PS/2 Keyboard, PS/2 Mice, Floppy Disk Controller, and the Trusted Platform Module