Interrupts Tutorial: Difference between revisions
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[[Category:Tutorials]] |
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Every operating system that needs to work with the hardware must have a set of interrupts. First, you need to learn about interrupts and how they work. http://www.osdever.net/tutorials/view/irqs is a good resource to check. This tutorial will tell you how to set up and use interrupts. |
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Every operating system that needs to work with the hardware (efficiently) must make use of interrupts. For example, you could use the entirety of an AP to poll the mouse, or you could use the mouse IRQs instead and save much more CPU time, and a lot of electrical load. Therefore, every reasonable operating system makes use of interrupts. |
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==IDT table== |
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When an interrupt is fired, the CPU looks at the IDT table, and finds what method needs to be called. Here, we build the IDT table as an array, and load it using the function "lidt" |
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<source lang="c"> |
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struct IDT_entry{ |
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unsigned short int offset_lowerbits; |
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unsigned short int selector; |
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unsigned char zero; |
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unsigned char type_attr; |
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unsigned short int offset_higherbits; |
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}; |
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==Pre-requisites== |
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struct IDT_entry IDT[256]; |
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Before you create an IDT, you need to create a [[GDT]], load it properly, and configure the segment registers accordingly. |
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</source> |
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Now, we need to remap the PIC (Programmable Interrupt Controller) and fill the IDT with the correct values. |
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<source lang="c"> |
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void idt_init(void) { |
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extern int load_idt(); |
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extern int irq0(); |
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extern int irq1(); |
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extern int irq2(); |
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extern int irq3(); |
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extern int irq4(); |
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extern int irq5(); |
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extern int irq6(); |
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extern int irq7(); |
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extern int irq8(); |
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extern int irq9(); |
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extern int irq10(); |
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extern int irq11(); |
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extern int irq12(); |
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extern int irq13(); |
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extern int irq14(); |
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extern int irq15(); |
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==[[Interrupt Descriptor Table]]== |
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unsigned long irq0_address; |
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===Entries=== |
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unsigned long irq1_address; |
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In order to make use of interrupts, you need an IDT. |
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unsigned long irq2_address; |
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unsigned long irq3_address; |
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unsigned long irq4_address; |
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unsigned long irq5_address; |
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unsigned long irq6_address; |
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unsigned long irq7_address; |
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unsigned long irq8_address; |
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unsigned long irq9_address; |
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unsigned long irq10_address; |
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unsigned long irq11_address; |
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unsigned long irq12_address; |
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unsigned long irq13_address; |
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unsigned long irq14_address; |
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unsigned long irq15_address; |
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unsigned long idt_address; |
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unsigned long idt_ptr[2]; |
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When an interrupt is fired, the CPU uses the vector as an index into the IDT. The CPU reads the entry of the IDT in order to figure out what to do prior to calling the [[ISR]], and what the address of the handler is. |
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/* remapping the PIC */ |
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outb(0x20, 0x11); |
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outb(0xA0, 0x11); |
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outb(0x21, 0x20); |
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outb(0xA1, 40); |
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outb(0x21, 0x04); |
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outb(0xA1, 0x02); |
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outb(0x21, 0x01); |
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outb(0xA1, 0x01); |
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outb(0x21, 0x0); |
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outb(0xA1, 0x0); |
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This is the structure of a single (32-bit) IDT entry: |
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irq0_address = (unsigned long)irq0; |
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<source lang="c"> |
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IDT[32].offset_lowerbits = irq0_address & 0xffff; |
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typedef struct { |
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IDT[32].selector = 0x08; /* KERNEL_CODE_SEGMENT_OFFSET */ |
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uint16_t isr_low; // The lower 16 bits of the ISR's address |
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IDT[32].zero = 0; |
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uint16_t kernel_cs; // The GDT segment selector that the CPU will load into CS before calling the ISR |
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IDT[32].type_attr = 0x8e; /* INTERRUPT_GATE */ |
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uint8_t reserved; // Set to zero |
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IDT[32].offset_higherbits = (irq0_address & 0xffff0000) >> 16; |
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uint8_t attributes; // Type and attributes; see the IDT page |
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uint16_t isr_high; // The higher 16 bits of the ISR's address |
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irq1_address = (unsigned long)irq1; |
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} __attribute__((packed)) idt_entry_t; |
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IDT[33].offset_lowerbits = irq1_address & 0xffff; |
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IDT[33].selector = 0x08; /* KERNEL_CODE_SEGMENT_OFFSET */ |
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IDT[33].zero = 0; |
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IDT[33].type_attr = 0x8e; /* INTERRUPT_GATE */ |
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IDT[33].offset_higherbits = (irq1_address & 0xffff0000) >> 16; |
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irq2_address = (unsigned long)irq2; |
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IDT[34].offset_lowerbits = irq2_address & 0xffff; |
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IDT[34].selector = 0x08; /* KERNEL_CODE_SEGMENT_OFFSET */ |
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IDT[34].zero = 0; |
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IDT[34].type_attr = 0x8e; /* INTERRUPT_GATE */ |
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IDT[34].offset_higherbits = (irq2_address & 0xffff0000) >> 16; |
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irq3_address = (unsigned long)irq3; |
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IDT[35].offset_lowerbits = irq3_address & 0xffff; |
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IDT[35].selector = 0x08; /* KERNEL_CODE_SEGMENT_OFFSET */ |
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IDT[35].zero = 0; |
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IDT[35].type_attr = 0x8e; /* INTERRUPT_GATE */ |
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IDT[35].offset_higherbits = (irq3_address & 0xffff0000) >> 16; |
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irq4_address = (unsigned long)irq4; |
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IDT[36].offset_lowerbits = irq4_address & 0xffff; |
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IDT[36].selector = 0x08; /* KERNEL_CODE_SEGMENT_OFFSET */ |
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IDT[36].zero = 0; |
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IDT[36].type_attr = 0x8e; /* INTERRUPT_GATE */ |
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IDT[36].offset_higherbits = (irq4_address & 0xffff0000) >> 16; |
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irq5_address = (unsigned long)irq5; |
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IDT[37].offset_lowerbits = irq5_address & 0xffff; |
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IDT[37].selector = 0x08; /* KERNEL_CODE_SEGMENT_OFFSET */ |
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IDT[37].zero = 0; |
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IDT[37].type_attr = 0x8e; /* INTERRUPT_GATE */ |
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IDT[37].offset_higherbits = (irq5_address & 0xffff0000) >> 16; |
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irq6_address = (unsigned long)irq6; |
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IDT[38].offset_lowerbits = irq6_address & 0xffff; |
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IDT[38].selector = 0x08; /* KERNEL_CODE_SEGMENT_OFFSET */ |
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IDT[38].zero = 0; |
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IDT[38].type_attr = 0x8e; /* INTERRUPT_GATE */ |
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IDT[38].offset_higherbits = (irq6_address & 0xffff0000) >> 16; |
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irq7_address = (unsigned long)irq7; |
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IDT[39].offset_lowerbits = irq7_address & 0xffff; |
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IDT[39].selector = 0x08; /* KERNEL_CODE_SEGMENT_OFFSET */ |
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IDT[39].zero = 0; |
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IDT[39].type_attr = 0x8e; /* INTERRUPT_GATE */ |
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IDT[39].offset_higherbits = (irq7_address & 0xffff0000) >> 16; |
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irq8_address = (unsigned long)irq8; |
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IDT[40].offset_lowerbits = irq8_address & 0xffff; |
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IDT[40].selector = 0x08; /* KERNEL_CODE_SEGMENT_OFFSET */ |
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IDT[40].zero = 0; |
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IDT[40].type_attr = 0x8e; /* INTERRUPT_GATE */ |
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IDT[40].offset_higherbits = (irq8_address & 0xffff0000) >> 16; |
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irq9_address = (unsigned long)irq9; |
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IDT[41].offset_lowerbits = irq9_address & 0xffff; |
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IDT[41].selector = 0x08; /* KERNEL_CODE_SEGMENT_OFFSET */ |
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IDT[41].zero = 0; |
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IDT[41].type_attr = 0x8e; /* INTERRUPT_GATE */ |
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IDT[41].offset_higherbits = (irq9_address & 0xffff0000) >> 16; |
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irq10_address = (unsigned long)irq10; |
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IDT[42].offset_lowerbits = irq10_address & 0xffff; |
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IDT[42].selector = 0x08; /* KERNEL_CODE_SEGMENT_OFFSET */ |
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IDT[42].zero = 0; |
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IDT[42].type_attr = 0x8e; /* INTERRUPT_GATE */ |
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IDT[42].offset_higherbits = (irq10_address & 0xffff0000) >> 16; |
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irq11_address = (unsigned long)irq11; |
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IDT[43].offset_lowerbits = irq11_address & 0xffff; |
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IDT[43].selector = 0x08; /* KERNEL_CODE_SEGMENT_OFFSET */ |
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IDT[43].zero = 0; |
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IDT[43].type_attr = 0x8e; /* INTERRUPT_GATE */ |
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IDT[43].offset_higherbits = (irq11_address & 0xffff0000) >> 16; |
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irq12_address = (unsigned long)irq12; |
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IDT[44].offset_lowerbits = irq12_address & 0xffff; |
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IDT[44].selector = 0x08; /* KERNEL_CODE_SEGMENT_OFFSET */ |
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IDT[44].zero = 0; |
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IDT[44].type_attr = 0x8e; /* INTERRUPT_GATE */ |
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IDT[44].offset_higherbits = (irq12_address & 0xffff0000) >> 16; |
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irq13_address = (unsigned long)irq13; |
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IDT[45].offset_lowerbits = irq13_address & 0xffff; |
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IDT[45].selector = 0x08; /* KERNEL_CODE_SEGMENT_OFFSET */ |
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IDT[45].zero = 0; |
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IDT[45].type_attr = 0x8e; /* INTERRUPT_GATE */ |
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IDT[45].offset_higherbits = (irq13_address & 0xffff0000) >> 16; |
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irq14_address = (unsigned long)irq14; |
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IDT[46].offset_lowerbits = irq14_address & 0xffff; |
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IDT[46].selector = 0x08; /* KERNEL_CODE_SEGMENT_OFFSET */ |
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IDT[46].zero = 0; |
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IDT[46].type_attr = 0x8e; /* INTERRUPT_GATE */ |
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IDT[46].offset_higherbits = (irq14_address & 0xffff0000) >> 16; |
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irq15_address = (unsigned long)irq15; |
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IDT[47].offset_lowerbits = irq15_address & 0xffff; |
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IDT[47].selector = 0x08; /* KERNEL_CODE_SEGMENT_OFFSET */ |
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IDT[47].zero = 0; |
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IDT[47].type_attr = 0x8e; /* INTERRUPT_GATE */ |
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IDT[47].offset_higherbits = (irq15_address & 0xffff0000) >> 16; |
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/* fill the IDT descriptor */ |
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idt_address = (unsigned long)IDT ; |
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idt_ptr[0] = (sizeof (struct IDT_entry) * 256) + ((idt_address & 0xffff) << 16); |
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idt_ptr[1] = idt_address >> 16 ; |
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load_idt(idt_ptr); |
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} |
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</source> |
</source> |
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and this is the structure of a single (64-bit) IDT entry: |
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Here are the IRQ handlers in assembly |
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<source lang="c"> |
<source lang="c"> |
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typedef struct { |
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global irq0 |
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uint16_t isr_low; // The lower 16 bits of the ISR's address |
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global irq1 |
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uint16_t kernel_cs; // The GDT segment selector that the CPU will load into CS before calling the ISR |
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global irq2 |
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uint8_t ist; // The IST in the TSS that the CPU will load into RSP; set to zero for now |
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global irq3 |
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uint8_t attributes; // Type and attributes; see the IDT page |
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global irq4 |
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uint16_t isr_mid; // The higher 16 bits of the lower 32 bits of the ISR's address |
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global irq5 |
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uint32_t isr_high; // The higher 32 bits of the ISR's address |
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global irq6 |
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uint32_t reserved; // Set to zero |
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global irq7 |
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} __attribute__((packed)) idt_entry_t; |
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global irq8 |
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global irq9 |
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global irq10 |
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global irq11 |
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global irq12 |
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global irq13 |
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global irq14 |
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global irq15 |
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global load_idt |
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global irq0_handler |
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global irq1_handler |
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global irq2_handler |
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global irq3_handler |
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global irq4_handler |
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global irq5_handler |
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global irq6_handler |
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global irq7_handler |
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global irq8_handler |
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global irq9_handler |
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global irq10_handler |
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global irq11_handler |
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global irq12_handler |
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global irq13_handler |
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global irq14_handler |
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global irq15_handler |
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extern irq0_handler |
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extern irq1_handler |
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extern irq2_handler |
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extern irq3_handler |
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extern irq4_handler |
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extern irq5_handler |
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extern irq6_handler |
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extern irq7_handler |
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extern irq8_handler |
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extern irq9_handler |
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extern irq10_handler |
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extern irq11_handler |
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extern irq12_handler |
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extern irq13_handler |
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extern irq14_handler |
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extern irq15_handler |
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irq0: |
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pusha |
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call irq0_handler |
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popa |
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iret |
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irq1: |
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pusha |
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call irq1_handler |
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popa |
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iret |
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irq2: |
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pusha |
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call irq2_handler |
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popa |
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iret |
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irq3: |
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pusha |
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call irq3_handler |
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popa |
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iret |
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irq4: |
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pusha |
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call irq4_handler |
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popa |
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iret |
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irq5: |
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pusha |
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call irq5_handler |
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popa |
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iret |
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irq6: |
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pusha |
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call irq6_handler |
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popa |
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iret |
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irq7: |
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pusha |
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call irq7_handler |
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popa |
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iret |
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irq8: |
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pusha |
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call irq8_handler |
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popa |
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iret |
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irq9: |
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pusha |
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call irq9_handler |
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popa |
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iret |
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irq10: |
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pusha |
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call irq10_handler |
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popa |
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iret |
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irq11: |
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pusha |
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call irq11_handler |
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popa |
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iret |
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irq12: |
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pusha |
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call irq12_handler |
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popa |
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iret |
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irq13: |
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pusha |
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call irq13_handler |
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popa |
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iret |
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irq14: |
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pusha |
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call irq14_handler |
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popa |
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iret |
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irq15: |
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pusha |
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call irq15_handler |
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popa |
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iret |
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load_idt: |
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mov edx, [esp + 4] |
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lidt [edx] |
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sti |
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ret |
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</source> |
</source> |
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===Table=== |
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And here are the IRQ handlers in C, which are called from the assembly code. We must send the EOI (End of Interrupt) signal to the PIC, to tell it that we're done handling the interrupt. If we dont, the PIC will think that we're still busy, and won't send any more IRQs. |
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To create an IDT, simply create a 256-entry array of descriptors: |
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<source lang="c"> |
<source lang="c"> |
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__attribute__((aligned(0x10))) |
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void irq0_handler(void) { |
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static idt_entry_t idt[256]; // Create an array of IDT entries; aligned for performance |
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outb(0x20, 0x20); //EOI |
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</source> |
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} |
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You will also need a special IDTR structure, which looks like: |
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<source lang="c"> |
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typedef struct { |
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uint16_t limit; |
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uint32_t base; |
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} __attribute__((packed)) idtr_t; |
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</source> |
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for a 32-bit IDT, or like: |
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<source lang="c"> |
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typedef struct { |
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uint16_t limit; |
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uint64_t base; |
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} __attribute__((packed)) idtr_t; |
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</source> |
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for a 64-bit IDT. |
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Don't forget to define an IDTR: |
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void irq1_handler(void) { |
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<source lang="c"> |
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outb(0x20, 0x20); //EOI |
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static idtr_t idtr; |
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} |
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</source> |
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===ISRs=== |
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void irq2_handler(void) { |
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In a C source file, define a general exception handler: |
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outb(0x20, 0x20); //EOI |
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<source lang="c"> |
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__attribute__((noreturn)) |
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void exception_handler(void); |
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void exception_handler() { |
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__asm__ volatile ("cli; hlt"); // Completely hangs the computer |
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} |
} |
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</source> |
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This will act as your main exception handler. When you receive a CPU exception, this is the handler you will call. |
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Now, in an assembly file ('''nasm''' '''assembler''' specifically), define these two macros: |
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void irq3_handler(void) { |
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<source lang="asm"> |
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outb(0x20, 0x20); //EOI |
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%macro isr_err_stub 1 |
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} |
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isr_stub_%+%1: |
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call exception_handler |
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iret |
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%endmacro |
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; if writing for 64-bit, use iretq instead |
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%macro isr_no_err_stub 1 |
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isr_stub_%+%1: |
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call exception_handler |
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iret |
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%endmacro |
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</source> |
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Then, use these macros to define your 32 exception handlers: |
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<source lang="asm"> |
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extern exception_handler |
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isr_no_err_stub 0 |
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isr_no_err_stub 1 |
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isr_no_err_stub 2 |
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isr_no_err_stub 3 |
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isr_no_err_stub 4 |
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isr_no_err_stub 5 |
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isr_no_err_stub 6 |
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isr_no_err_stub 7 |
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isr_err_stub 8 |
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isr_no_err_stub 9 |
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isr_err_stub 10 |
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isr_err_stub 11 |
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isr_err_stub 12 |
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isr_err_stub 13 |
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isr_err_stub 14 |
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isr_no_err_stub 15 |
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isr_no_err_stub 16 |
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isr_err_stub 17 |
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isr_no_err_stub 18 |
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isr_no_err_stub 19 |
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isr_no_err_stub 20 |
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isr_no_err_stub 21 |
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isr_no_err_stub 22 |
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isr_no_err_stub 23 |
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isr_no_err_stub 24 |
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isr_no_err_stub 25 |
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isr_no_err_stub 26 |
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isr_no_err_stub 27 |
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isr_no_err_stub 28 |
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isr_no_err_stub 29 |
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isr_err_stub 30 |
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isr_no_err_stub 31 |
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</source> |
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Finally, in assembly, define a "stub table". (This is used to prevent excessive code reuse, and not related to actual function.) |
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Using NASM macros: |
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void irq4_handler(void) { |
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<source lang="asm"> |
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outb(0x20, 0x20); //EOI |
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global isr_stub_table |
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} |
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isr_stub_table: |
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%assign i 0 |
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%rep 32 |
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dd isr_stub_%+i ; use DQ instead if targeting 64-bit |
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%assign i i+1 |
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%endrep |
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</source> |
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===Assembling=== |
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Finally, we can assemble the IDT: |
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We need to |
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* 1. Assign the IDT entries with the correct values, |
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* 2. Reload the IDTR register, |
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* 3. Set the interrupt flag. |
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To define the entries, it is appropriate to make use of a helper function. That helper function would look like: |
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void irq5_handler(void) { |
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<source lang="c"> |
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outb(0x20, 0x20); //EOI |
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void idt_set_descriptor(uint8_t vector, void* isr, uint8_t flags); |
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} |
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void idt_set_descriptor(uint8_t vector, void* isr, uint8_t flags) { |
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idt_entry_t* descriptor = &idt[vector]; |
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descriptor->isr_low = (uint32_t)isr & 0xFFFF; |
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void irq6_handler(void) { |
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descriptor->kernel_cs = 0x08; // this value can be whatever offset your kernel code selector is in your GDT |
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outb(0x20, 0x20); //EOI |
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descriptor->attributes = flags; |
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descriptor->isr_high = (uint32_t)isr >> 16; |
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descriptor->reserved = 0; |
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} |
} |
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</source> |
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for a 32-bit IDT, or like: |
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<source lang="c"> |
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void idt_set_descriptor(uint8_t vector, void* isr, uint8_t flags); |
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void idt_set_descriptor(uint8_t vector, void* isr, uint8_t flags) { |
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idt_desc_t* descriptor = &idt[vector]; |
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descriptor->base_low = (uint64_t)isr & 0xFFFF; |
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void irq7_handler(void) { |
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descriptor->cs = GDT_OFFSET_KERNEL_CODE; |
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outb(0x20, 0x20); //EOI |
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descriptor->ist = 0; |
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descriptor->attributes = flags; |
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descriptor->base_mid = ((uint64_t)isr >> 16) & 0xFFFF; |
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descriptor->base_high = ((uint64_t)isr >> 32) & 0xFFFFFFFF; |
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descriptor->rsv0 = 0; |
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} |
} |
||
</source> |
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for a 64-bit IDT. |
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Finally, to set the entries at last, this is what the function would look like: |
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void irq8_handler(void) { |
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<source lang="c"> |
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outb(0xA0, 0x20); |
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extern void* isr_stub_table[]; |
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outb(0x20, 0x20); //EOI |
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} |
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void |
void idt_init(void); |
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void idt_init() { |
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outb(0xA0, 0x20); |
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idtr.base = (uintptr_t)&idt[0]; |
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outb(0x20, 0x20); //EOI |
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idtr.limit = (uint16_t)sizeof(idt_desc_t) * IDT_MAX_DESCRIPTORS - 1; |
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} |
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for (uint8_t vector = 0; vector < 32; vector++) { |
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void irq10_handler(void) { |
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idt_set_descriptor(vector, isr_stub_table[vector], 0x8E, 1); |
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outb(0xA0, 0x20); |
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vectors[vector] = true; |
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} |
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} |
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__asm__ volatile ("lidt %0" : : "memory"(idtr)); // load the new IDT |
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void irq11_handler(void) { |
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__asm__ volatile ("sti"); // set the interrupt flag |
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outb(0xA0, 0x20); |
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outb(0x20, 0x20); //EOI |
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} |
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void irq12_handler(void) { |
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outb(0xA0, 0x20); |
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outb(0x20, 0x20); //EOI |
|||
} |
|||
void irq13_handler(void) { |
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outb(0xA0, 0x20); |
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outb(0x20, 0x20); //EOI |
|||
} |
|||
void irq14_handler(void) { |
|||
outb(0xA0, 0x20); |
|||
outb(0x20, 0x20); //EOI |
|||
} |
|||
void irq15_handler(void) { |
|||
outb(0xA0, 0x20); |
|||
outb(0x20, 0x20); //EOI |
|||
} |
} |
||
</source> |
</source> |
||
Congratulations! You have successfully defined your IDT, loaded it, and enabled interrupts. |
|||
==What to do next== |
|||
Now you can write your handler methods! |
|||
After completing this tutorial, there is still much left for you to do to fully harness the power of interrupts. |
|||
==Interrupts in GRUB== |
|||
If you use GRUB as your bootloader, after setting up the IDT emulators, you will get a fatal error. This is most likely due to the fact that you haven't set up the GDT. Here is some the assembly code to example how you can set it. You should set the GDT before IDT, best in bootloader. |
|||
<source lang="asm"> |
|||
jmp load_gdt |
|||
;global descriptor table |
|||
gdt: |
|||
gdt_null: |
|||
dq 0 |
|||
gdt_code: |
|||
dw 0FFFFh |
|||
dw 0 |
|||
db 0 |
|||
db 10011010b |
|||
db 11001111b |
|||
db 0 |
|||
gdt_data: |
|||
dw 0FFFFh |
|||
dw 0 |
|||
db 0 |
|||
db 10010010b |
|||
db 11001111b |
|||
db 0 |
|||
gdt_end: |
|||
gdt_desc: |
|||
dw gdt_end - gdt - 1 |
|||
dd gdt |
|||
;load gdt |
|||
load_gdt: |
|||
cli ;disable interrupts |
|||
lgdt [gdt_desc] ;load GDT |
|||
sti ;enable interrupts |
|||
</source> |
|||
I have tested this code and it works in both Virtualbox and QEMU. Good luck! |
|||
Klakap |
|||
You can: |
|||
* Initialize the [[PIC]] |
|||
* Make use of PIC [[IRQ]]s |
|||
* Understand the [[NMI]] |
|||
* Configure the local [[APIC]] |
|||
* Write a driver for the [[IOAPIC]] |
|||
* Make use of [[Message Signaled Interrupts]] |
|||
==See also== |
==See also== |
||
===Threads=== |
===Threads=== |
||
* [https://forum.osdev.org/viewtopic.php?f=1&t=33160&p=285871#p285871 Interrupts |
* [https://forum.osdev.org/viewtopic.php?f=1&t=33160&p=285871#p285871 Interrupts don't work in GRUB] |
||
===References=== |
===References=== |
||
* [https://github.com/rizet/skylight/blob/trunk/glass/src/cpu/interrupts/idt.c The code this tutorial is based off of] |
|||
* [https://arjunsreedharan.org/post/99370248137/kernel-201-lets-write-a-kernel-with-keyboard Kernel 201] |
Revision as of 20:48, 30 May 2021
Difficulty level |
---|
![]() Beginner |
Every operating system that needs to work with the hardware (efficiently) must make use of interrupts. For example, you could use the entirety of an AP to poll the mouse, or you could use the mouse IRQs instead and save much more CPU time, and a lot of electrical load. Therefore, every reasonable operating system makes use of interrupts.
Pre-requisites
Before you create an IDT, you need to create a GDT, load it properly, and configure the segment registers accordingly.
Interrupt Descriptor Table
Entries
In order to make use of interrupts, you need an IDT.
When an interrupt is fired, the CPU uses the vector as an index into the IDT. The CPU reads the entry of the IDT in order to figure out what to do prior to calling the ISR, and what the address of the handler is.
This is the structure of a single (32-bit) IDT entry:
typedef struct {
uint16_t isr_low; // The lower 16 bits of the ISR's address
uint16_t kernel_cs; // The GDT segment selector that the CPU will load into CS before calling the ISR
uint8_t reserved; // Set to zero
uint8_t attributes; // Type and attributes; see the IDT page
uint16_t isr_high; // The higher 16 bits of the ISR's address
} __attribute__((packed)) idt_entry_t;
and this is the structure of a single (64-bit) IDT entry:
typedef struct {
uint16_t isr_low; // The lower 16 bits of the ISR's address
uint16_t kernel_cs; // The GDT segment selector that the CPU will load into CS before calling the ISR
uint8_t ist; // The IST in the TSS that the CPU will load into RSP; set to zero for now
uint8_t attributes; // Type and attributes; see the IDT page
uint16_t isr_mid; // The higher 16 bits of the lower 32 bits of the ISR's address
uint32_t isr_high; // The higher 32 bits of the ISR's address
uint32_t reserved; // Set to zero
} __attribute__((packed)) idt_entry_t;
Table
To create an IDT, simply create a 256-entry array of descriptors:
__attribute__((aligned(0x10)))
static idt_entry_t idt[256]; // Create an array of IDT entries; aligned for performance
You will also need a special IDTR structure, which looks like:
typedef struct {
uint16_t limit;
uint32_t base;
} __attribute__((packed)) idtr_t;
for a 32-bit IDT, or like:
typedef struct {
uint16_t limit;
uint64_t base;
} __attribute__((packed)) idtr_t;
for a 64-bit IDT.
Don't forget to define an IDTR:
static idtr_t idtr;
ISRs
In a C source file, define a general exception handler:
__attribute__((noreturn))
void exception_handler(void);
void exception_handler() {
__asm__ volatile ("cli; hlt"); // Completely hangs the computer
}
This will act as your main exception handler. When you receive a CPU exception, this is the handler you will call.
Now, in an assembly file (nasm assembler specifically), define these two macros:
%macro isr_err_stub 1
isr_stub_%+%1:
call exception_handler
iret
%endmacro
; if writing for 64-bit, use iretq instead
%macro isr_no_err_stub 1
isr_stub_%+%1:
call exception_handler
iret
%endmacro
Then, use these macros to define your 32 exception handlers:
extern exception_handler
isr_no_err_stub 0
isr_no_err_stub 1
isr_no_err_stub 2
isr_no_err_stub 3
isr_no_err_stub 4
isr_no_err_stub 5
isr_no_err_stub 6
isr_no_err_stub 7
isr_err_stub 8
isr_no_err_stub 9
isr_err_stub 10
isr_err_stub 11
isr_err_stub 12
isr_err_stub 13
isr_err_stub 14
isr_no_err_stub 15
isr_no_err_stub 16
isr_err_stub 17
isr_no_err_stub 18
isr_no_err_stub 19
isr_no_err_stub 20
isr_no_err_stub 21
isr_no_err_stub 22
isr_no_err_stub 23
isr_no_err_stub 24
isr_no_err_stub 25
isr_no_err_stub 26
isr_no_err_stub 27
isr_no_err_stub 28
isr_no_err_stub 29
isr_err_stub 30
isr_no_err_stub 31
Finally, in assembly, define a "stub table". (This is used to prevent excessive code reuse, and not related to actual function.)
Using NASM macros:
global isr_stub_table
isr_stub_table:
%assign i 0
%rep 32
dd isr_stub_%+i ; use DQ instead if targeting 64-bit
%assign i i+1
%endrep
Assembling
Finally, we can assemble the IDT: We need to
- 1. Assign the IDT entries with the correct values,
- 2. Reload the IDTR register,
- 3. Set the interrupt flag.
To define the entries, it is appropriate to make use of a helper function. That helper function would look like:
void idt_set_descriptor(uint8_t vector, void* isr, uint8_t flags);
void idt_set_descriptor(uint8_t vector, void* isr, uint8_t flags) {
idt_entry_t* descriptor = &idt[vector];
descriptor->isr_low = (uint32_t)isr & 0xFFFF;
descriptor->kernel_cs = 0x08; // this value can be whatever offset your kernel code selector is in your GDT
descriptor->attributes = flags;
descriptor->isr_high = (uint32_t)isr >> 16;
descriptor->reserved = 0;
}
for a 32-bit IDT, or like:
void idt_set_descriptor(uint8_t vector, void* isr, uint8_t flags);
void idt_set_descriptor(uint8_t vector, void* isr, uint8_t flags) {
idt_desc_t* descriptor = &idt[vector];
descriptor->base_low = (uint64_t)isr & 0xFFFF;
descriptor->cs = GDT_OFFSET_KERNEL_CODE;
descriptor->ist = 0;
descriptor->attributes = flags;
descriptor->base_mid = ((uint64_t)isr >> 16) & 0xFFFF;
descriptor->base_high = ((uint64_t)isr >> 32) & 0xFFFFFFFF;
descriptor->rsv0 = 0;
}
for a 64-bit IDT.
Finally, to set the entries at last, this is what the function would look like:
extern void* isr_stub_table[];
void idt_init(void);
void idt_init() {
idtr.base = (uintptr_t)&idt[0];
idtr.limit = (uint16_t)sizeof(idt_desc_t) * IDT_MAX_DESCRIPTORS - 1;
for (uint8_t vector = 0; vector < 32; vector++) {
idt_set_descriptor(vector, isr_stub_table[vector], 0x8E, 1);
vectors[vector] = true;
}
__asm__ volatile ("lidt %0" : : "memory"(idtr)); // load the new IDT
__asm__ volatile ("sti"); // set the interrupt flag
}
Congratulations! You have successfully defined your IDT, loaded it, and enabled interrupts.
What to do next
After completing this tutorial, there is still much left for you to do to fully harness the power of interrupts.
You can:
- Initialize the PIC
- Make use of PIC IRQs
- Understand the NMI
- Configure the local APIC
- Write a driver for the IOAPIC
- Make use of Message Signaled Interrupts