Instruction Set Architecture: Difference between revisions

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==Hybrid Instruction Set==
==Hybrid Instruction Set==


RISC-processors can be build more easier and clocked faster. Any modern CPU is build uppon a RISC. But one do not want missing the advanced instruction a CISC provides. So a hybrid is build. The RISC is used as ALU and is wrapped by a CISC environment. Any instruction is interpreted by this CISC and is splitted in one or more subcode instructions, so called microopcodes, for the RISC. Additionally the CISC-wrap promise security and operating system stability and contoll. Nowadays only microcontroller are pure RISCs, any other CPU is more or less a hybrid RISC-CISC CPU.
Modern CPUs are built upon a hybrid RISC-CISC architecture. RISC processors can be built more easily and clocked faster, but lack the advanced instructions of a CISC. To get the best of both worlds, a hybrid is built. A RISC is used as the ALU, and is wrapped by a CISC environment. Any instruction is interpreted by this CISC and is split into one or more sub-instructions, called "micro-opcodes", for the RISC. Additionally, the CISC-wrapping provides security, along with operating system stability and control. Nowadays, only microcontrollers are pure RISCs; any other CPU is more or less a hybrid RISC-CISC CPU.
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