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ISA DMA: Difference between revisions
Added a comment about master and slave controllers
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== Technical Details ==
Each 8237 DMA chip has 4 DMA channels. DMA0-DMA3 on the first chip and DMA4-DMA7 on the second. The first DMA controller is wired up for 8 bit transfers,
while the second is wired up for 16 bit transfers. On some tutorials or other wiki articles, you will sometimes see the '''second''' DMA chip (channels 4 to 7) labeled as the "'''master'''" controller, and the first (channels 0 to 3) called the "slave". This is highly confusing, and these terms will not be used again, here.
DMA Channel 0 is unavailable as it was used for a short time for DRAM memory refresh, and remains reserved because of this (even though modern computers
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* MMT and ADHE. Did you know that the IBM PC could do memory to memory transfers since 1981? That's right, hardware sprites, hardware frame buffering from one location to another. Does it work? No.
* COND. Hooray the only bit in the control register that does something useful. Setting this bit disables the DMA controller. This is one way to set up multiple DMA channels without masking each and every channel.
;Request Registers 0x09 and 0xD2 (Write)
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