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ISA DMA: Difference between revisions
added a little bit of clarity about masking DRQ
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interrupt. This implies that all peripherals using an ISA DMA channel are limited to no more than 64 KB transfers for fear of upsetting the DMA controller.
Even with the PC/AT, IBM began bypassing the ISA DMA used in the PC/XT and used
was because of the 64 KB limitations outlined above and the fact that the 286 processor could perform 16 bit transactions at 6 MHz. Even the ISA bus could
run at a speed of up to 12 MHz, far faster than the 4.77 MHz the DMA controller was running at.
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This creates two serious problems. One is "contention issues". The other is that it is difficult to be sure what state the flip-flop is currently in.
The standard solution for dealing with the flip-flop state issue is to reset the flip-flop to "low byte" state every single time you want to use it, just
so you can be certain it is in the proper state before sending bytes. There are only two solutions to "contention": either use a
one ISA DMA driver, so that contention is impossible.
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interrupt when a transfer completes. However, some peripherals may '''not''' send an interrupt if a transfer fails with an error. As always, timeouts
are important.
=== The Registers ===
The master and slave DMA controllers are very similar, so (to save space) both of them have been combined into the following table. Please try
not to let this confuse you.
Note: for Address and Count Registers on channels 5 to 7, see
▲Note: for Address and Count Registers on channels 5 to 7, see [[#16 bit issues|16 bit issues]] above.
Each 8237A has 18 registers, addressed via the I/O Port bus:
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|0xC0
|Word
|
|Start Address Register channel 0/4 (unusable)
|-
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;Single Channel Mask Registers 0x0A and 0xD4 (Write)
{| {{wikitable}}
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If you do not want to figure out the mask states of all the other channels, you can mask/unmask one channel at a time with this register.▼
These registers are used to mask (or unmask) DRQ for a single channel only, on either the master or slave DMA chip.
▲
Use the SEL 0 and 1 bits to select the channel, and the MASK_ON bit to set or clear masking for it.
Note that masking DMA channel 4 will mask 7, 6, 5 and 4 due to cascading.
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Setting the appropriate bits to 0 or 1 allows you to unmask or mask (
to know the desired mask states of ''all'' the channels at that moment. There are several ways to do this, but one is simply to read this register, first.
Note that masking DMA channel 4 will mask 7, 6, 5 and 4 due to cascading.
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* MMT and ADHE. Did you know that the IBM PC could do memory to memory transfers since 1981? That's right, hardware sprites, hardware frame buffering from one location to another. Does it work? No.
* COND. Hooray the only bit in the control register that does something useful. Setting this bit disables the DMA controller. This is one way to set up multiple DMA channels without masking each and every channel.
HIHI!! is PRIO=0 BAD? PRIO=1?
;Request Registers 0x09 and 0xD2 (Write)
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<source lang="asm">
<pre>
initialize_floppy_DMA:
; set DMA channel 2 to transfer data from 0x1000 - 0x33ff in memory
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out 0x0a, 0x01 ; unmask DMA channel 2
ret
</pre>
</source>
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<source lang="asm">
<pre>
prepare_for_floppy_DMA_write:
out 0x0a, 0x05 ; mask DMA channel 2 and 0
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out 0x0a, 0x01 ; unmask DMA channel 2
ret
</pre>
</source>
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