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made tables from <pre>'s
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Each 8237A has 5 registers addressed via I/O space
Each 8237A has 5 registers addressed via I/O space


{| {{wikitable}}
<pre>
|-
8237A No. 1 8237A No. 2 Read or Write Function
!8237A No. 1
Address Address
!8237A No. 2
0x08 0xD0 R Status Register
|
0x08 0xD0 W Command Register
|
0x09 0xD2 W Request Register
|-
0x0A 0XD4 W DMA Channel Mask Register
!Address
0x0B 0xD6 W DMA Mode Register
!Address
0x0C 0XD8 R Byte / Word Register
!Read or Write
0x0D 0xDA R Intermediate Register
!Function
0x0F 0XDE W DMA Mask Register
|-
</pre>
|0x08
|0xD0
|R
|Status Register
|-
|0x08
|0xD0
|W
|Command Register
|-
|0x09
|0xD2
|W
|Request Register
|-
|0x0A
|0XD4
|W
|DMA Channel Mask Register
|-
|0x0B
|0xD6
|W
|DMA Mode Register
|-
|0x0C
|0XD8
|R
|Byte / Word Register
|-
|0x0D
|0xDA
|R
|Intermediate Register
|-
|0x0F
|0XDE
|W
|DMA Mask Register
|-
|}


Each DMA Channel has an External Page Address Register that is added to the upper 8 bits of the DMA transfer address
Each DMA Channel has an External Page Address Register that is added to the upper 8 bits of the DMA transfer address


{| {{wikitable}}
<pre>
|-
0x87 DMA Channel 0 Page Address Register (bits A17 - A24)
|0x87
0x83 DMA Channel 1 Page Address Register (bits A17 - A24)
0x82 DMA Channel 2 Page Address Register (bits A17 - A24)
|DMA Channel 0 Page Address Register (bits A17 - A24)
|-
0x81 DMA Channel 3 Page Address Register (bits A17 - A24)
|0x83
0x8F DMA Channel 4 Page Address Register (bits A17 - A24)
0x8B DMA Channel 5 Page Address Register (bits A17 - A24)
|DMA Channel 1 Page Address Register (bits A17 - A24)
|-
0x89 DMA Channel 6 Page Address Register (bits A17 - A24)
|0x82
0x8A DMA Channel 7 Page Address Register (bits A17 - A24)
|DMA Channel 2 Page Address Register (bits A17 - A24)
</pre>
|-
|0x81
|DMA Channel 3 Page Address Register (bits A17 - A24)
|-
|0x8F
|DMA Channel 4 Page Address Register (bits A17 - A24)
|-
|0x8B
|DMA Channel 5 Page Address Register (bits A17 - A24)
|-
|0x89
|DMA Channel 6 Page Address Register (bits A17 - A24)
|-
|0x8A
|DMA Channel 7 Page Address Register (bits A17 - A24)
|-
|}


(Bit Patterns from Indispensable PC Hardware Book - I'm commenting the useful parts i.e. the bits you can actually use, a lot of the 'features' of the 8237 do not function in the PC and the fact they do not work introduces new 'features'. Please assume that if anything isn't explicitly mentioned, it implicitly does not function. Messing with things not mentioned will usually result in screwing up of your computer. Don't take my word for it (I could be Kermit the Frog for all you know!) so feel free to ask other people and do whatever makes you feel good.)
(Bit Patterns from Indispensable PC Hardware Book - I'm commenting the useful parts i.e. the bits you can actually use, a lot of the 'features' of the 8237 do not function in the PC and the fact they do not work introduces new 'features'. Please assume that if anything isn't explicitly mentioned, it implicitly does not function. Messing with things not mentioned will usually result in screwing up of your computer. Don't take my word for it (I could be Kermit the Frog for all you know!) so feel free to ask other people and do whatever makes you feel good.)


Status Registers 0x08 and 0xD0 (Read)
;Status Registers 0x08 and 0xD0 (Read)
{| {{wikitable}}

|-
<pre>
|Bit 7
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
|Bit 6
REQ3 REQ2 REQ1 REQ0 TC3 TC2 TC1 TC0
|Bit 5
</pre>
|Bit 4
|Bit 3
|Bit 2
|Bit 1
|Bit 0
|-
|REQ3
|REQ2
|REQ1
|REQ0
|TC3
|TC2
|TC1
|TC0
|}




Line 126: Line 199:




Command Registers 0x08 and 0xD0 (Write)
;Command Registers 0x08 and 0xD0 (Write)
{| {{wikitable}}

|-
<pre>
|Bit 7
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
|Bit 6
DACKP DRQP EXTW PRIO COMP COND ADHE MMT
|Bit 5
</pre>
|Bit 4
|Bit 3
|Bit 2
|Bit 1
|Bit 0
|-
|DACKP
|DRQP
|EXTW
|PRIO
|COMP
|COND
|ADHE
|MMT
|}


This register really shows how incompatible the 8237 is with the PC hardware.
This register really shows how incompatible the 8237 is with the PC hardware.
Line 139: Line 227:
COND. Hooray the only bit in the control register that does something useful. Setting this bit disables the DMA controller. This lets you set up multiple DMA channels without masking each and every channel.
COND. Hooray the only bit in the control register that does something useful. Setting this bit disables the DMA controller. This lets you set up multiple DMA channels without masking each and every channel.


Request Registers 0x09 and 0xD2 (Write)
;Request Registers 0x09 and 0xD2 (Write)
:Used for memory to memory transfers and setting up priority rotation- absolutely useless.


;DMA Channel Mask Registers 0x0A and 0xD4 (Write)
Used for memory to memory transfers and setting up priority rotation- absolutely useless.


{| {{wikitable}}
DMA Channel Mask Registers 0x0A and 0xD4 (Write)
|-

|Bit 7
<pre>
|Bit 6
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
|Bit 5
STCL SEL1 SEL 0
|Bit 4
</pre>
|Bit 3
|Bit 2
|Bit 1
|Bit 0
|-
|
|
|
|
|
|STCL
|SEL1
|SEL 0
|}


To mask a channel for programming / whatever set STCL to 1 and SEL0 and SEL1 to select the channel to be masked
To mask a channel for programming / whatever set STCL to 1 and SEL0 and SEL1 to select the channel to be masked
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This register only allows you to mask / unmask a '''SINGLE''' DMA channel if you need to mask multiple DMA channels you need to use -
This register only allows you to mask / unmask a '''SINGLE''' DMA channel if you need to mask multiple DMA channels you need to use -


DMA Mask Registers 0x0F and 0xDE (Write)
;DMA Mask Registers 0x0F and 0xDE (Write)
{| {{wikitable}}

|-
<pre>
|Bit 7
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
|Bit 6
STC3 STC2 STC1 STC0
|Bit 5
</pre>
|Bit 4
|Bit 3
|Bit 2
|Bit 1
|Bit 0
|-
|
|
|
|
|STC3
|STC2
|STC1
|STC0
|}


Setting the appropriate bits to 0 or 1 allows you to mask or unmask those channels.
Setting the appropriate bits to 0 or 1 allows you to mask or unmask those channels.
Line 167: Line 285:
due to cascading.
due to cascading.


DMA Mode Registers 0x0B and 0xD6 (Write)
;DMA Mode Registers 0x0B and 0xD6 (Write)
{| {{wikitable}}

|-
<pre>
|Bit 7
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
|Bit 6
MOD1 MOD0 IDEC AUTO TRA1 TRA0 SEL1 SEL0
|Bit 5
</pre>
|Bit 4
|Bit 3
|Bit 2
|Bit 1
|Bit 0
|-
|MOD1
|MOD0
|IDEC
|AUTO
|TRA1
|TRA0
|SEL1
|SEL0
|}


This register is tricky as it depends highly on the peripheral you are programming the DMA controller for.
This register is tricky as it depends highly on the peripheral you are programming the DMA controller for.


*SEL0 and SEL1 selects the channel you want to change.
<pre>
SEL0 and SEL1 selects the channel you want to change.
*TRA0 and TRA1 selects the transfer type.
**00 runs a self test of the controller.
TRA0 and TRA1 selects the transfer type.
**01 DMA Channel is for writing to memory
00 runs a self test of the controller.
01 DMA Channel is for writing to memory
**10 DMA Channel is for reading from memory
**11 invalid
10 DMA Channel is for reading from memory
11 invalid
</pre>


AUTO. When this bit is set, after a transfer has completed the channel resets itself to the values you programmed into it.
AUTO. When this bit is set, after a transfer has completed the channel resets itself to the values you programmed into it.
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To reset the flip-flop write anything to the register :-
To reset the flip-flop write anything to the register :-


ASM :
;ASM
out 0xd8, 0xFF
out 0xd8, 0xFF


C :
;C
<pre>
<pre>
void reset_flipflop_DMA()
void reset_flipflop_DMA()
Line 230: Line 361:
Writing anything to this register (0x0d) resets all count, address and mask values ready for you to program.
Writing anything to this register (0x0d) resets all count, address and mask values ready for you to program.


ASM :
;ASM
out 0x0d, 0xFF
out 0x0d, 0xFF
;reinitialize all DMA channels now
;reinitialize all DMA channels now


C :
;C
<pre>
<pre>
void hard_reset_DMA()
void hard_reset_DMA()
Line 245: Line 376:
Writing anything to this register (0xdc) will clear the mask register (wow!) releasing all DMA channels to accept DMA requests.
Writing anything to this register (0xdc) will clear the mask register (wow!) releasing all DMA channels to accept DMA requests.


ASM :
;ASM
out 0xdc, 0xFF
out 0xdc, 0xFF
; reinitialize all DMA channels now
; reinitialize all DMA channels now


C :
;C
<pre>
<pre>
void unmask_all_DMA()
void unmask_all_DMA()
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