IA32 Architecture Family: Difference between revisions

The biggest competitor to Intel at this time (2004 August). They came into being slightly after Cyrix with a 5k86 (being a 486 compatible similar to the 5x86, don't confuse them) and then followed it up by a K6 processor. This one was faster than the Pentiums, and more popular than the Cyrix ones because they both didn't rate it (afaik), and they didn't overheat (as was claimed, untrue, for the Cyrixes).

It is important to note that the "SSE" used by AMD and the "SSE" used by Intel are actually not compatible, not fully at least (somebody verify this?). This causes lots of confusion.

| AMD's 486 clone turned out a success for being on-par with Intel's processors, while being a lot cheaper. Eventually, the higher-clocked Am5x86 was the fastest processor to fit in on a 486-based motherboard. Together with its 4x multiplier and 2x the cache size of most Intel's 486 chips, it was able to outperform the low end of Pentium chips.

| AMD's first try at a Pentium-compatible CPU. Not a huge success, mostly due to low clock speeds.

| Actually designed by NexGen (who AMD took over), the K6 is a fully Pentium-compatible CPU. It outperformed the Pentium in several areas. One notable instruction was the LOOPcc instruction, which executed in 2 cycles compared to a Pentium's 18, causing problems.

| AMD had a lesson learned there, don't make your processor too fast in some instructions. Not that they were put off by that, they just added 16 wait states to the execution of the LOOPcc and thus caused it to slow to the speed of a Pentium. AMD didn't just do this however. They added a special case (speculation, might be coincidence) for the DEC (E)CX; Jcc combination, which is semantically equivalent with the LOOPcc instruction, but this semantic equivalence and the loop being faster on Intels caused the loop instruction to always be used. Nobody used the DEC/Jcc combo. They kept the original speed for this combo and specified in their optimization manuals that this was the preferred method over the loopcc instruction.

It also featured a new technology, the 3DNOW! technology, which was MMX using floating point numbers, and multiplexed (again) on the floating point registers. The K6-2 was quite popular, and scaled higher than the P1 ever did. It was largely compatible with the P2, but (afaik) not completely.

| They started this design off with the concept of not making it underpowered in any place, and to make it at least P2 compatible. It was fully P2 compatible.

The K6-3 was not too popular, mainly because the K6-2 did very well and people didn't see why they should buy a more expensive K6-3 for the same amount of megahertz. This of course was a joke, same as it is to call a 2 GHz opteron slower than a 2.2 GHz celeron.

A little known fact about the K6-3 is that it is in fact an Athlon, minus a few instructions, and minus one very important piece. The K6-3 suffered from a bottleneck at the instruction decode unit (which converts the X86 instructions to native instructions). It could only handle 2 in a cycle, which it made during about 20-30% of the cycles for average software. For optimized software you could bring it to 100% easily, and still want another channel. This wasn't too weird, because it did have 3 execution units of each type (ALU / MMX / loadstore) which were not used much at all. Note that these units are units executing the native instructions, so making 3 of each is not a stupid idea. They needed a new front end, and of course a new copy of instructions from Intel.

| Athlon XP (..starting with Palomino) introduced SSE, SMP capable chips were branded as Athlon MP.

===Athlon (first try)===

The first models of the Athlon were distinct, they were the first time that a competitor to Intel actually had a faster processor, without Intel having a backup plan. It was poised against the PIII, which at that time was their top model and best-running one too. The Athlon beat them to the 1 GHz mark, and at that time the 1 GHz had become completely irrelevant. It just meant that they had a new size to mark their processors with. Intel missed the point here, and they did until very shortly ago. The GHz myth had been broken, the Athlon at 1.1 GHz was still faster than the PIII at 1.3 GHz, and people knew. They didn't go for a P3 if a faster athlon was available at a lower clock speed, and at a lower price.

===Athlon XP / MP / Duron (new style)===

AMD switched to a big offensive, trying to persuade the buyers to demand AMD CPU's instead of being OK with Intels. The new versions of these processors were all just a tad better than the previous one, could do a slight number of instructions more (the Athlons started with not even SSE1, and from model 6 (both Athlon and Duron) they supported it). The processors also advanced very slightly in each other direction, making each new type just a tad faster than the previous one. In the end of the GHz wars (past year, about) the fastest Athlon was running at 2.2 GHz, but outperformed the better half of the 3 GHz P4's.

This is slightly offtopic here, but still quite relevant, since these processors all support the entire IA32 family natively. AMD created a new processor, with 64-bit (actually 48-bit, but who notices those 16 bits?) memory addressing and 64-bit calculations, being very compatible with the old style CPU's. So compatible, that the core for 32-bit and 64-bit is essentially equal, aside from the size of calculations and the support of a few encodings that were in effect redundant. They removed a few 1-byte opcodes (about 20 in total, including all 1-byte INC and 1-byte DEC instructions) to make place for a new REX prefix. They modified it to use 16 registers instead of 8, added a load of new names, got the old software working, and optimized the 32-bit performance to unprecedented levels. These CPU's outperform the P4 at any clock speed, in almost (1/20 programs not) any calculation-intensive program.