HPET: Difference between revisions
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==Preface== |
==Preface== |
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HPET, or High Precision Event Timer, is a piece of hardware designed by Intel and Microsoft to replace older [[PIT]] and [[RTC]]. It consists of (usually 64-bit) main counter (which counts up), as well as from 3 to |
HPET, or High Precision Event Timer, is a piece of hardware designed by Intel and Microsoft to replace older [[PIT]] and [[RTC]]. It consists of (usually 64-bit) main counter (which counts up), as well as from 3 to 32 32 or 64 bit wide comparators. HPET is programmed using memory mapped IO, and the base address of HPET can be found using [[ACPI]]. |
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==Detecting HPET using ACPI== |
==Detecting HPET using ACPI== |
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==HPET - timer vs comparators== |
==HPET - timer vs comparators== |
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There is just one up counting main counter in the timer, but interrupt generation is handled by *comparators*. There' |
There is just one up counting main counter in the timer, but interrupt generation is handled by *comparators*. There're from 3 to 32 comparators, and the exact amount is indicated by <code>comparator_count</code> field in the above <code>hpet</code> structure. Keep in mind you have to initialize both the main counter and all of the comparators. Also, the routing as well as '''allowed''' routing of comparator interrupts is independent, so you have to detect and set it up for each of them individually. More information on this procedure is provided further in the text. |
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==HPET operating modes== |
==HPET operating modes== |
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===General Interrupt Status Register=== |
===General Interrupt Status Register=== |
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{| {{wikitable}} |
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!Bits |
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!Name |
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!Description |
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|- |
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|63:32 |
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|Reserved |
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| - |
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|- |
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|n |
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|Tn_INT_STS |
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|The functionality is dependent of whether edge or level-triggered mode is used for timer #n. |
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'''For level-triggered:''' the default value is 0. When a corresponding timer interrupt is active, this bit is set. If it is set, software can clear it by writing 1 to this bit. Writes of 0 have no effect. |
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'''For edge-triggered:''' this bit should be ignored. It is always set to 0. |
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|} |
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===Main Counter Value Register=== |
===Main Counter Value Register=== |
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Bits 63:0 of this register are called MAIN_COUNTER_VAL. Writes to this register should only be done when the counter is halted (ENABLE_CNF = 0). Reads will return current value of the main counter. 32-bit counters will always return 0 for the upper 32 bits. If 32 bit reads are performed on 64 bit counter, consult 2.4.7 in the specification for instructions how to do it safely. It is recommended to use 32 bit counter when on 32-bit only software. |
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===Timer N Configuration and Capability Register=== |
===Timer N Configuration and Capability Register=== |
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{| {{wikitable}} |
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!Bits |
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!Name |
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!Description |
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|- |
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|63:32 |
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|Tn_INT_ROUTE_CAP |
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|Timer n Interrupt Routing Capability. If bit X is set in this field, it means that this timer can be mapped to IRQX line of I/O APIC. |
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|- |
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|31:16 |
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|Reserved |
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| - |
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|- |
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|15 |
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|Tn_FSB_INT_DEL_CAP |
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|If this read-only bit is 1, this timer supports FSB interrupt mapping. |
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|- |
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|14 |
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|Tn_FSB_EN_CNF |
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|If this bit is set to 1, this timer will use FSB interrupt mapping. |
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|- |
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|13:9 |
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|Tn_INT_ROUTE_CNF |
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|This field indicates I/O APIC routing. Allowed values can be determined using Tn_INT_ROUTE_CAP. If an illegal value is written, then value read back from this field will not match the written value. |
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|- |
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|8 |
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|Tn_32MODE_CNF |
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|For 64-bit timer, if this field is set, the timer will be forced to work in 32-bit mode. Otherwise it has no effect. |
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|- |
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|7 |
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|Reserved |
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| - |
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|- |
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|6 |
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|Tn_VAL_SET_CNF |
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|This field is used to allow software to directly set periodic timer's accumulator. Detailed explanation is provided further in the article. |
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|- |
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|5 |
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|Tn_SIZE_CAP |
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|If this read-only bit is set to 1, the size of the timer is 64-bit. Otherwise, it's 32-bit. |
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|- |
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|4 |
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|Tn_PER_INT_CAP |
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|If this read-only bit is set to 1, this timer supports periodic mode. |
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|- |
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|3 |
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|Tn_TYPE_CNF |
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|If Tn_PER_INT_CAP is 1, then writing 1 to this field enables periodic timer and writing 0 enables non-periodic mode. Otherwise, this bit will be ignored and reading it will always return 0. |
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|- |
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|2 |
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|Tn_INT_ENB_CNF |
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|Setting this bit to 1 enables triggering of interrupts. Even if this bit is 0, this timer will still set Tn_INT_STS. |
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|- |
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|1 |
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|Tn_INT_TYPE_CNF |
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|0 - this timer generates edge-triggered interrupts. |
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1 - this timer generates level-triggered interrupts. When the interrupt is generated, Tn_INT_STS is set. If another interrupt occurs before that bit is cleared, the interrupt will remain active. |
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|- |
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|0 |
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|Reserved |
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| - |
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|} |
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===Timer N Comparator Value Register=== |
===Timer N Comparator Value Register=== |
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Bits 63:0 (or 31:0, if the timer operates in 32 bit mode) are used to compare with main counter to check if an interrupt should be generated. |
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==See also== |
==See also== |
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