Global Descriptor Table: Difference between revisions
Jump to navigation
Jump to search
[unchecked revision] | [unchecked revision] |
Content deleted Content added
Revolution (talk | contribs) |
Revolution (talk | contribs) No edit summary |
||
Line 123: | Line 123: | ||
== System Segment Descriptor == |
== System Segment Descriptor == |
||
For system segments, such as those defining a '''[[Task State Segment]]''' or '''Local Descriptor Table''', the format of the '''Access Byte''' differs slightly, in order to define different types of system segments rather than code and data segments. |
For system segments, such as those defining a '''[[Task State Segment]]''' or '''[[Local Descriptor Table]]''', the format of the '''Access Byte''' differs slightly, in order to define different types of system segments rather than code and data segments. |
||
For more information, see '''Section 3.5: System Descriptor Types''' and '''Figure 3-2: System-Segment and Gate-Descriptor Types''' of the Intel Software Developer Manual, Volume 3-A. |
For more information, see '''Section 3.5: System Descriptor Types''' and '''Figure 3-2: System-Segment and Gate-Descriptor Types''' of the Intel Software Developer Manual, Volume 3-A. |
||
Line 158: | Line 158: | ||
== 64-bit System Segment Descriptor == |
== 64-bit System Segment Descriptor == |
||
For a '''[[Task State Segment]]''' or '''Local Descriptor Table''' in '''[[Long Mode]]''', the format of a '''Segment Descriptor''' differs to ensure that the '''Base''' value can contain a 64-bit '''[[Linear Address]]'''. It takes up the space in the table of two usual entries, in a little endian format, such that the lower half of this entry precedes the higher half in the table. |
For a '''[[Task State Segment]]''' or '''[[Local Descriptor Table]]''' in '''[[Long Mode]]''', the format of a '''Segment Descriptor''' differs to ensure that the '''Base''' value can contain a 64-bit '''[[Linear Address]]'''. It takes up the space in the table of two usual entries, in a little endian format, such that the lower half of this entry precedes the higher half in the table. |
||
For more information, see '''Section 7.2.3: TSS Descriptor in 64-bit Mode''' and '''Figure 7-4: Format of TSS and LDT Descriptors in 64-bit Mode''' of the Intel Software Developer Manual, Volume 3-A. |
For more information, see '''Section 7.2.3: TSS Descriptor in 64-bit Mode''' and '''Figure 7-4: Format of TSS and LDT Descriptors in 64-bit Mode''' of the Intel Software Developer Manual, Volume 3-A. |