Global Descriptor Table: Difference between revisions
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Revolution (talk | contribs) I felt this article could use somewhat of a rewrite as I found its formatting confusing and information kind of garbled (particularly information pertaining to 64-bit mode). Feel free to change formatting or wholly revert the edit if not welcome. |
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The '''Global Descriptor Table''' ('''GDT''') is specific to the [[IA32_Architecture_Family |IA32 |
The '''Global Descriptor Table''' ('''GDT''') is a binary data structure specific to the [[IA32_Architecture_Family |IA32]] and [[X86-64 |x86-64]] architectures. It contains entries telling the CPU about memory [[Segmentation|segments]]. A similar [[Interrupt Descriptor Table]] exists containing [[task]] and [[Interrupts|interrupt]] descriptors. Read the [[GDT Tutorial]]. |
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== Structure == |
== Structure == |
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=== GDTR === |
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The GDT is loaded using the |
The '''GDT''' is pointed to by the value in the '''GDTR''' register. This is loaded using the '''LGDT''' assembly instruction, whose argument is a pointer to a '''GDT Descriptor''' structure: |
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[[Image:Gdtr.png|frame|center|GDTR]] |
[[Image:Gdtr.png|frame|center|GDTR]] |
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* '''Size:''' The size of the table in bytes subtracted by 1. This subtraction occurs because the maximum value of '''Size''' is 65535, while the '''GDT''' can be up to 65536 bytes in length (8192 entries). Further, no '''GDT''' can have a size of 0 bytes. |
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* '''Offset:''' The linear address of the '''GDT''' (not the physical address, paging applies). |
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Note that the amount of data loaded by '''LGDT''' differs in 32-bit and 64-bit modes, the offset is 4 bytes long in 32-bit mode and 8 bytes long in 64-bit mode. |
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For more information, see '''Section 2.4.1: Global Descriptor Table Register (GDTR)''' and '''Figure 2-6: Memory Management Registers''' of the Intel Software Developer Manual, Volume 3-A. |
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---- |
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Here is the structure of the access byte and flags: |
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=== Segment Descriptor === |
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The bit fields are: |
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What "Limit 0:15" means is that the field contains bits 0-15 of the '''Limit''' value. |
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* '''S:''' Descriptor type. This bit should be set for code or data segments and should be cleared for system segments (eg. a [[Task_State_Segment|Task State Segment]]) |
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* '''Base:''' A 32-bit value containing the linear address where the segment begins. |
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In 64-bit mode, the '''Base''' and '''Limit''' values are ignored, each descriptor covers the entire linear address space regardless of what they are set to. |
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The '''Access Byte''' and '''Flags''' are laid out as follows: |
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'''Access Byte:''' |
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* '''S:''' Descriptor type bit. If clear ('''0''') the descriptor defines a system segment (eg. a [[Task_State_Segment|Task State Segment]]). If set ('''1''') it defines a code or data segment. |
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* '''Ex:''' Executable bit. If clear ('''0''') the descriptor defines a data segment. If set ('''1''') it defines a code segment which can be executed from. |
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* '''DC:''' Direction bit/Conforming bit. |
* '''DC:''' Direction bit/Conforming bit. |
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** |
** For data selectors: Direction bit. If clear ('''0''') the segment grows up. If set ('''1''') the segment [[Expand_Down|grows down]], ie. the '''Offset''' has to be greater than the '''Limit'''. |
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** |
** For code selectors: Conforming bit. |
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*** If '''1''' code in this segment can be executed from an equal or lower privilege level. |
*** If set ('''1''') code in this segment can be executed from an equal or lower privilege level. For example, code in ring 3 can far-jump to ''conforming'' code in a ring 2 segment. The '''Privl''' field represent the highest privilege level that is allowed to execute the segment. For example, code in ring 0 cannot far-jump to a conforming code segment where '''Privl''' is 2, while code in ring 2 and 3 can. Note that the privilege level remains the same, ie. a far-jump from ring 3 to a segment with a '''Privl''' of 2 remains in ring 3 after the jump. |
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*** If '''0''' code in this segment can only be executed from the ring set in <tt>privl</tt>. |
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* '''RW:''' Readable bit/Writable bit. |
* '''RW:''' Readable bit/Writable bit. |
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** Readable bit |
** For code segments: Readable bit. If clear ('''0'''), read access for this segment is not allowed. If set ('''1''') read access is allowed. Write access is never allowed for code segments. |
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** |
** For data segments: Writeable bit. If clear ('''0'''), write access for this segment is not allowed. If set ('''1''') write access is allowed. Read access is always allowed for data segments. |
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* '''Ac:''' Accessed bit. |
* '''Ac:''' Accessed bit. Best left clear ('''0'''), the CPU will set it when the segment is accessed. |
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'''Flags:''' |
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* '''L:''' Long-mode code flag. If set ('''1'''), the descriptor defines a 64-bit code segment. When set, '''Sz''' should always be clear. For any other type of segment (other code types or any data segment), it should be clear ('''0'''). |
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** The diagram currently does not reflect its position, it is bit-53 of the overall descriptor or one bit to the right of the '''Sz''' bit in this diagram. |
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For more information, see '''Section 3.4.5: Segment Descriptors''' and '''Figure 3-8: Segment Descriptor''' of the Intel Software Developer Manual, Volume 3-A. |
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=== x86-64 Changes === |
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* '''L''' bit (bit 53, next to '''Sz''') is used to indicate x86-64 code descriptor. '''For data segments, this bit is reserved''' |
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* '''Sz''' bit (bit 54) has to be 0 when the '''L''' bit is set, as the combination '''Sz''' = 1, '''L''' = 1 is reserved for future use (and will throw an exception if you try to use it) |
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<br/> |
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The [[LGDT]] instruction will look for a 8-byte base address in long mode. |
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<br/> |
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See Figure 3-8, "Segment Descriptor" of the Intel System Programmer's manual. |
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== See also == |
== See also == |