GDT Tutorial: Difference between revisions

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In the [[:Category:x86|Intel Architecture]], and more precisely in [[protected mode]], most of the [[memory management]] and [[Interrupt Service Routines]] are controlled through tables of descriptors. Each descriptor stores information about a single object (e.g. a service routine, a task, a chunk of code or data, whatever) the CPU might need at some time. If you try, for instance, to load a new value into a [[Segment|segment register]], the CPU needs to perform safety and access control checks to see whether you're actually entitled to access that specific memory area. Once the checks are performed, useful values (such as the lowest and highest addresses) are cached in invisible registers of the CPU.

: a memory structure (part of a table) that tells the CPU the attributes of a given segment

=== Basics ===