Floppy Disk Controller: Difference between revisions

More detailed info can be found in the [[ATA in x86 RealMode (BIOS)]] article, because accessing a floppy is identical to accessing a hard disk

(using CHS) in Real Mode. The rest of this article deals with creating Protected Mode drivers for the floppy subsystem.

=== Accessing USB Floppy Drives ===

If you are using PIO mode in a singletasking environment then the IRQ6s just waste CPU cycles, and you should be using polling instead.

To do PIO data transfers: init/reset the controller if needed (see below), select the drive if needed (see below),

There were several generations of floppy controller chips on several generations of 80286 (and prior) computers, before

the 82077AA chip existed. The 82077AA was built to emulate all of them, by setting various pins on the chip to 5 volts.

In the documentation, you can ignore PC-AT mode. Or you can try to handle all three, by only using registers and commands that are identical

in all 3 modes.

On real hardware, there are definite timing issues. Seek delays and motor delays are just what any programmer would expect. It

would be nice if the drive would send an IRQ when the motor was up to speed, but it does not. Two things that you may not

== Registers ==

=== Bitflags and Registers that you can rely on ===

As said above, the most common controller chip has 3 modes, and many bitflags in the registers are different (or opposite!) depending on

FIFO: The FIFO register may not have a 16byte buffer in all modes, but this is a minor difference that does not really affect its operation.

TDR: The Tape Drive Register is identical in all modes, but it is useless (you will never find functional equipment that requires it).

The two important bits are RQM and DIO. NDMA and BUSY are also useful in polling PIO mode.

Most important is RQM, which is set when it is OK (or necessary!) to read/write data from/to the FIFO port.

NDMA signals the end of the "execution phase" of a command, and the beginning of "result phase".

==== CCR and DSR ====

use different datarates, then you need to switch the datarate when you select the other drive. It also seems to be possible

to modify this register while the FDC is in "reset state".

Datarates used for setting either DSR or CCR:

Note: There is also a 300Kbps (value = 1), and a 250Kbps setting (value = 2) but they are only for utterly obsolete drives/media.

==== DIR register, Disk Change bit ====

== Programming Details ==

accessed. To do that, you:

# Turn on the drive's motor and select the drive, using an "outb" command to the DOR IO port.

# Issue your command byte plus some parameter bytes (the "command phase") to the FIFO IO port.

# Exchange data with the drive / "seek" the drive heads (the "execution phase"), on the FIFO IO port.

can completely lock up some systems. This claim seems unlikely?

needed for data transfer. The controller has electronics to handle a large variation in rotation speed, but it has its limits.

If you start reading/writing immediately after the motor is turned on, "the PLL will fail to lock on to the data signal" and you will get an error.

to seek the heads back to cylinder 0 just before turning the motor off.) You could leave the motor on longer,

The suggested delays when turning the motor on are:

## Bit 2 (value = 4) in the DOR: Save the current/"original" value of the DOR, write a 0 to the DOR, wait 4 microseconds, then write the original value (bit 2 is always set) back to the DOR.

## '''or''' Bit 7 (value = 0x80) in the DSR: Precalculate a good value for the DSR (generally 0), and OR it with 0x80. Write that value to the DSR.

# Send a Sense Interrupt command (required).

# If your OS/driver never turned off polling mode (see the Configure command), then you have to send 3 more Sense Interrupt commands. (Alternately, you can tell if you need the extra 3 by examining the top 2 bits of the st0 byte returned by the first Sense Interrupt. If both bits are set, you need to send 3 more.)

command fails -- this may be the reason why.

==== Waiting ====

## Loop on reading MSR until RQM = 1, verify that DIO = 1.

## In a loop: read the next result byte from the FIFO, loop on reading MSR until RQM = 1, verify CMD BSY = 1 and DIO = 1 ((Value & 0x50) == 0x50).

Note: implementing a failure timeout for each loop and the IRQ is pretty much required -- it is the only way to detect many command errors.

==== Status Registers ====

There are 3 registers that hold information about the last error encountered. The st0 register information

===== st0 =====

===== st1 =====

The st1 register provides more detail about errors during read/write operations.

caused by '''not subtracting 1''' when setting the DMA byte count.

Bit 4 (value = 0x10) is set if your driver is too slow to get bytes in or out of the FIFO port in time.

===== st2 =====

==== Configure ====

(And "Write Precompensation".) A good setting is: implied seek on, FIFO on, polling off, threshold = 8, precompensation 0.

===== SRT, HLT and HUT =====

controller were always meant

to be '''adaptive'''. That is, your driver is theoretically supposed to keep statistics of how often Seek commands fail with the current

setting of SRT. If they always work, and your driver wants to optimize performance, then it can send a new Specify command, with the SRT

Keeping statistics in that way only works when the drive in question is used often. Now that internal floppy drives are nearly obsolete,

Note: if you try to read the result bytes without waiting for RQM to set, then you are likely to always get an incorrect result value

==== Recalibrate ====

A Sense Interrupt command is required after this command completes, to clear it from being BUSY. (Multiple Sense Interrupts,

if you ran multiple Seeks.)

===== Relative seek =====

==== Read/Write ====

Note: Remember that this is in CHS format, so the sector number starts at 1.

Note2: Floppy media and electronics are well known for being unreliable. Any read or write command that fails should be retried

=== Perpendicular Mode and 2.88M floppies ===

If you are using an emulator and you need a floppy disk image that is bigger than 1440Kb, there is a 2880Kb image available.

In order to access it in Pmode, you need to modify your driver to handle Perpendicular Mode. Basically, it is an extra configuration

You also need to set CCR/DSR for the 1M datarate (value = 3) to access a 2.88M drive.

== Code Examples ==